Prosecution Insights
Last updated: July 17, 2026
Application No. 18/605,859

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Mar 15, 2024
Priority
Aug 14, 2023 — TW 112130494
Examiner
HARRISTON, WILLIAM A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Orient Semiconductor Electronics Limited
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
953 granted / 1066 resolved
+21.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
65.6%
+25.6% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Information Disclosure Statement The information disclosure statement filed on 04/17/2025 and 03/15/2024 have been considered. Drawings The drawings filed on 03/15/2024 are acceptable. Specification The abstract of the disclosure and the specification filed on 03/15/2024 are acceptable. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6 and 8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Tung (US 2022/0199428). PNG media_image1.png 382 564 media_image1.png Greyscale Regarding claim 1, Tung (US 2022/0199428) discloses: A method of manufacturing a semiconductor package, comprising: providing a first die (120, ¶0017) having opposing top surface and bottom surface; forming a plurality of first conductive bumps (130, ¶0017) on the top surface of the first die (120), wherein the first conductive bumps (130) are electrically connected to the first die (¶0017); adhering the first die to a heat spreader (150, ¶0023); forming a molding layer (170, ¶0024) on the heat spreader to cover the first conductive bumps (130) and the first die (120); grinding the molding layer (¶0026) to expose the first conductive bumps (130); and forming a redistribution layer (110, ¶0022) on the molding layer (170, ¶0026) to electrically connect to the first conductive bumps (130). Regarding claim 6, Tung further discloses: wherein the first conductive bumps are formed on the first die by a bumping process (¶0017). Regarding claim 8, Tung discloses: A semiconductor package, comprising: a heat spreader (150); a first die (120) disposed on the heat spreader (150), the first die having opposing top surface and bottom surface; a plurality of first conductive bumps (130) disposed on the top surface of the first die, wherein the first conductive bumps are electrically connected to the first die (120); a molding layer (170) formed on the heat spreader (170) to cover the top surface of the first die (120) and expose the first conductive bumps (130); and a redistribution layer (110) disposed on the molding layer (170) to electrically connect to the first conductive bumps (130, ¶0017). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 3, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung. Regarding claim 2, Tung does not disclose “a second die having opposing top surface and bottom surface; forming a plurality of second conductive bumps on the top surface of the second die, wherein the second conductive bumps are electrically connected to the second die; adhering the second die to the heat spreader; covering the second conductive bumps and the second die with the molding layer; exposing the second conductive bumps from the molding layer; and electrically connecting the redistribution layer to the second conductive bumps”. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to duplicate a semiconductor package as claimed since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art and has no patentable significance unless a new and unexpected result is produced. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. In reHarza, 274 F.2d 669, 124 USPQ 378. Regarding claim 9, Tung does not disclose “a second die disposed on the heat spreader, the second die having opposing top surface and bottom surface; and a plurality of second conductive bumps disposed on the top surface of the second die, wherein the second conductive bumps are electrically connected to the second die; wherein the molding layer further covers the top surface of the second die and exposes the second conductive bumps; and the redistribution layer is further electrically connected to the second conductive bumps”. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to duplicate a semiconductor package as claimed since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art and has no patentable significance unless a new and unexpected result is produced. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. In reHarza, 274 F.2d 669, 124 USPQ 378. Regarding claims 3 and 10, Tung does not disclose “wherein the heat spreader is a lead frame”. However, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). Therefore, as Tung teaches the claimed structure, the limitation is met. Allowable Subject Matter Claims 4, 5 and 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 4, the prior art does not disclose “4. The method as claimed in claim 1, wherein the first conductive bumps are formed on the first die by a wire bonding process using one of gold wires, copper wires and alloy wires” in combination with the remaining claimed features. Regarding claim 7, the prior art does not disclose “wherein the first die is adhered to the heat spreader after the first conductive bumps are formed on the first die” in combination with the remaining claimed features. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677641
SEMICONDUCTOR DEVICE
3y 7m to grant Granted Jul 07, 2026
Patent 12672568
SUBSTRATE HAVING AN INCREASED METAL TRACE THICKNESS
2y 11m to grant Granted Jun 30, 2026
Patent 12660564
PRINT-READY WAFERS WITH BOTTOM-ANCHORED COMPONENTS
3y 9m to grant Granted Jun 16, 2026
Patent 12653001
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND PATTERN FORMATION METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
4y 2m to grant Granted Jun 09, 2026
Patent 12648497
SEMICONDUCTOR PACKAGE USING SUBSTRATE BLOCK INTEGRATION
2y 11m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month