Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10 and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, hereinafter Liu498 (US 2016/0064498 A1) in view of Kim et al. (US 2021/0043629 A1).
Regarding independent claim 1: Liu498 teaches (e.g., Figs. 1A-2E) a semiconductor structure, comprising:
conductive layers ([0051]: 114b);
a first gate pillar ([0051]: 108) penetrating the conductive layers (114b).
Liu498 does not expressly teach
a first channel element surrounding the first gate pillar;
a first conductive strip on a sidewall of the first channel element; and
a charge storage structure on a surface of the first conductive strip.
Kim teaches (e.g., Figs. 1-2 and Figs. 23-24B; [0085]: “for concise description, an element previously described with reference to FIGS. 3 and 4A to 4E will be identified by the same reference number without repeating an overlapping description thereof”) a semiconductor structure comprising:
a first channel element ([0085]-[0086]: first channel from top to bottom; CH is the channel of the semiconductor pattern, SP; see [0031] and [0050]) surrounding a first gate pillar ([0052] and [0085]-[0086]: GE);
a first conductive strip ([0086]: first conductive strip, PAD from top to bottom) on a sidewall of the first channel element (CH); and
a charge storage structure ([0033] and [0053]: DS) on a surface of the first conductive strip (PAD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Liu498, the structure comprising a first channel element surrounding the first gate pillar; a first conductive strip on a sidewall of the first channel element; and a charge storage structure on a surface of the first conductive strip, for the benefits of manufacturing a more compact memory device and at the same time increasing the productivity by manufacturing more memory chips on the same substrate, thus more devices with smaller footprint allowing more portability is afforded.
Regarding claim 2: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 1, on which this claim depends, further comprising:
a second gate pillar (Liu498: [0042]-[0044]: left side gate pillar 108) penetrating the conductive layers,
wherein the first gate pillar (Liu498: [0042]-[0044]: right side gate pillar 108) is separated from the second gate pillar;
a second channel element (Kim: [0085]-[0086]: second channel from top to bottom; CH is the channel of the semiconductor pattern, SP; see [0031] and [0050]) surrounding the second gate pillar,
wherein the first channel element (Kim: [0085]-[0086]: first channel from top to bottom; CH) is separated from the second channel element (Kim: [0085]-[0086]: second channel from top to bottom; CH).
Regarding claim 8: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 1, on which this claim depends,
wherein the conductive layers (Liu498: [0051]: conductive layers 114b).
are functioned as bit lines ([0049] and [0051]: conductive layers 114b functions as bit lines; “the plurality of stack structures 114 (serving as a plurality of bit lines”)).
Regarding claim 9: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 1, on which this claim depends, further comprising:
a dielectric layer (Liu498: [0047] and [0049]: 116) surrounding the first gate pillar (Liu498: 108) and between the first gate pillar (Liu498: 108) and the first channel element (Kim: [0052] and [0085]-[0086]: CH).
Regarding claim 10: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 1, on which this claim depends.
Liu498 and Kim further teaches that the semiconductor structure comprises
a memory cell (Kim: [0027] and [0031]: MCT) comprising a transistor (Kim: [0024], [0027] and [0031]: transistor) and a capacitor (Kim: [0027], [0031] and [0033]: capacitor),
wherein the transistor (Kim: transistor including SP) forms at an intersection of the conductive layers (Kim: corresponding structure is BL, see [0025], [0034]-[0035] and [0045]-[0046]) and the first conductive strip (Kim: PAD), and
the first conductive strip (Kim: PAD) and the charge storage structure (Kim: [0033] and [0053]: DS) forms the capacitor (Kim: DS includes EL1, DL and EL2 which forms a capacitor).
Regarding independent claim 13: Liu498 teaches (e.g., Figs. 1A-2E) a method for manufacturing a semiconductor structure, comprising:
forming a first stack ([0051]: left side 114b) and a second stack ([0051]: right side 114b), wherein the second stack is on a sidewall of the first stack (Fig. 2E; [0051]);
forming a gate pillar ([0051]: 108) in the first stack,
forming bit lines ([0051]: 114b), wherein the gate pillar penetrating (108) the bit lines (114b).
Liu498 does not expressly teach
forming a channel element in the first stack;
wherein the channel element surrounds the gate pillar;
forming a conductive strip on a sidewall of the channel element; and
forming a charge storage structure on a surface of the conductive strip.
Kim teaches (e.g., Figs. Figs. 1-2 and 23-24B; [0085]: “for concise description, an element previously described with reference to FIGS. 3 and 4A to 4E will be identified by the same reference number without repeating an overlapping description thereof”) a method comprising
forming a channel element ([0085]-[0086]: first channel from top to bottom; CH is the channel of the semiconductor pattern, SP; see [0031] and [0050]) in a first stack (Fig. 23; [0049]: SS);
wherein the channel element (CH) surrounds a gate pillar ([0052] and [0085]-[0086]: GE);
forming a conductive strip ([0086]: first conductive strip, PAD from top to bottom) on a sidewall of the channel element (CH); and
forming a charge storage structure ([0033] and [0053]: DS) on a surface of the conductive strip (PAD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Liu498, the method comprising forming a channel element in the first stack; wherein the channel element surrounds the gate pillar; forming a conductive strip on a sidewall of the channel element; and forming a charge storage structure on a surface of the conductive strip, for the benefits of manufacturing a more compact memory device and at the same time increasing the productivity by manufacturing more memory chips on the same substrate, thus, manufacturing more devices with smaller footprint allowing more portability.
Regarding claim 14: Liu498 and Kim teach the claim limitation of the of the method according to claim 13, on which this claim depends, further comprising:
forming a hole (Kim: [0049], [0064]-[0066]: HO) in the first stack ([0049]: SS);
forming a recess is the first stack (Kim: [0049], [0064]-[0066]), wherein the recess and the hole communicates with each other (Fig. 24B; [0049], [0064]-[0066]),
wherein the channel element (Kim: CH) is formed in the recess, and the gate pillar (Kim: GE) is formed in the hole.
Regarding claim 15: Liu498 and Kim teach the claim limitation of the of the method according to claim 14, on which this claim depends,
wherein the recess exposes the second stack (Kim: [0049] and [0064]-[0066]).
Regarding claim 16: Liu498 and Kim teach the claim limitation of the of the method according to claim 14, on which this claim depends,
wherein the first stack comprises first insulating layers (Kim: [0056] and [0087]: STL) and second insulating layers (Kim: [0056] and [0079]: IL) stacked alternately (Kim: [0065]), and the recess is between the first insulating layers (Kim: [0056], [0084] and [0087]: STL)
Regarding claim 17: Liu498 and Kim teach the claim limitation of the of the method according to claim 16, on which this claim depends,
wherein the hole penetrates the first insulating layers (Kim: [0056], [0084] and [0087]: STL) and the second insulating layers (Kim: [0056] and [0079]: IL).
Regarding claim 18: Liu498 and Kim teach the claim limitation of the of the method according to claim 16, on which this claim depends,
wherein the first insulating layers comprise oxide (Kim: [0056], [0084] and [0087]: first insulating layers STL comprise silicon oxide), and the second insulating layers comprise nitride (Kim: [0056], [0063] and [0079]: IL comprises silicon nitride).
Regarding claim 19: Liu498 and Kim teach the claim limitation of the of the method according to claim 13, on which this claim depends, further comprising:
forming a plurality of the gate pillars (Liu498: [0051]: 108) in the first stack,
herein the channel element (Kim: CH) surrounds the plurality of the gate pillars (Kim: GE).
Claims 11-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, hereinafter Liu498 (US 2016/0064498 A1) in view of Kim et al. (US 2021/0043629 A1) as applied above and further in view Lee et al. (US 2021/0183861 A1).
Regarding claim 11: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 1, on which this claim depends.
Liu498 as modified by Kim does not expressly teach that the first channel element comprises an oxide semiconductor material.
Lee teaches (e.g., Figs. 1-4) a semiconductor structure comprising a first channel element ([0031] and [0044]);
Lee further teaches that the first channel element comprises an oxide semiconductor material ([0031] and [0044]: “the oxide semiconductor material may be, e.g., indium-gallium-zinc oxide (IGZO)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Liu498, the first channel element comprising and oxide semiconductor material, as taught by Lee, for the benefits of reducing power consumption and leakage current of the device.
Regarding claim 12: Liu498 and Kim teach the claim limitation of the of the semiconductor structure according to claim 11, on which this claim depends,
wherein the first channel element comprises first channel element comprises Indium oxide (InOx) and/or indium gallium zinc oxide (IGZO) (Lee: [0031] and [0044]: “the oxide semiconductor material may be, e.g., indium-gallium-zinc oxide (IGZO)”).
Regarding claim 20: Liu498 and Kim teach the claim limitation of the of the method according to claim 13, on which this claim depends,
wherein the channel element comprises an oxide semiconductor material.
Liu498 as modified by Kim does not expressly teach that the channel element comprises an oxide semiconductor material.
Lee teaches (e.g., Figs. 1-4) a method comprising forming a channel element ([0031] and [0044]);
Lee further teaches that the first channel element comprises an oxide semiconductor material ([0031] and [0044]: “the oxide semiconductor material may be, e.g., indium-gallium-zinc oxide (IGZO)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Liu498, the method of forming the channel element comprising an oxide semiconductor material, as taught by Lee, for the benefits of reducing power consumption and leakage current of the device.
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor structure comprising:
“wherein the conductive layers are disposed along a first direction and extend along a second direction perpendicular to the first direction, the first gate pillar and the second gate pillar are disposed along the second direction, and the first channel element and the second channel element are in the conductive layers”.
Claim 4 depends on claim 3, and therefore, is allowable for the same reason as claim 3.
Regarding claim 5: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor structure comprising:
“a second gate pillar penetrating the conductive layers, wherein the first gate pillar is separated from the second gate pillar, and the first channel element surrounds the first gate pillar and the second gate pillar”.
Claims 6-7 depend on claim 5, and therefore, are allowable for the same reason as claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
Prosecution Insights