DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 103 3
A. Claims 1-6, 8, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0083008 (“Igarashi”) in view of US 2023/081718 (“Iwayama”). 3
B. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi in view of Iwayama, as applied to claim 1 above, and further in view of US 2021/0257413 (“Kanaya”). 9
C. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi in view of Iwayama, as applied to claims 1 and 8, above, and further in view of US 2021/0184102 (“Lee”). 10
III. Response to Arguments 11
Conclusion 12
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-6, 8, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0083008 (“Igarashi”) in view of US 2023/081718 (“Iwayama”).
Each of the applied references has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome each of Igarashi and Iwayama as prior art available under 35 USC 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 1 reads,
1. (Currently Amended) A memory device comprising:
[1] a first wiring line extending along a first direction;
[2] a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction intersecting the first direction; and
[3a] a memory cell provided between the first wiring line and the second wiring line, and including
[3b] a magnetoresistance effect element, a switching element, a middle electrode provided between the magnetoresistance effect element and the switching element, and
[3c] and a resistive layer provided between the magnetoresistance effect element and the second wiring line,
[3d] wherein a resistance of the resistive layer is higher than a resistance of the middle electrode, and
[3e] the resistive layer is formed of a semiconductor material containing silicon (Si), germanium (Ge) or carbon (C).
With regard to claim 1, Igarashi discloses, generally in Figs. 6 and 9,
1. A memory device comprising:
[1] a first wiring line 50 extending along a first direction Y [¶ 49; Fig. 3];
[2] a second wiring line 51 [¶ 49; Fig. 3] provided on an upper layer side of the first wiring line 50 and extending along a second direction X intersecting the first direction Y; and
[3a] a memory cell MC [¶ 51; Fig. 3] provided between the first wiring line 50 and the second wiring line 51, and including
[3b] a magnetoresistance effect element 14/15/11/12/13 [¶¶ 71-84; Figs. 6, 9], a switching element 2 [¶¶ 64-70], a middle electrode 19A or 16/19A [¶¶ 83, 85-86] provided between the magnetoresistance effect element 14/15/11/12/13 and the switching element 2, and
[3c] and a resistive layer 17, 17A [¶¶ 91-92 and, generally ¶¶ 87-106, 139-151] provided between the magnetoresistance effect element 14/15/11/12/13 and the second wiring line 51,
[3d] wherein a resistance of the resistive layer 17, 17A is higher than a resistance of the middle electrode 19A or 16/19A [because 16 and 19A are conductive, while 17 and 17A are resistors], and
[3e] … [not taught] …
With regard to feature [3e] of claim 1 and claim 12,
[3e] the resistive layer is formed of a semiconductor material containing silicon (Si), germanium (Ge) or carbon (C).
12. (New) The memory device of claim 1, wherein the semiconductor material of the resistive layer further contains an n-type or p- type impurity.
Igarashi makes the resistive layer 17 from an oxide transition metal or lanthanoid metal (¶¶ 141-145), which is termed a band-gap material (¶ 145) and, correspondingly may be taken as a semiconductor material. However, Igarashi does not disclose that the resistive layer 17, recognized as a semiconductor, is made of the materials claimed in feature [3e] of claim 1 and claim 12.
Iwayama, like Igarashi, teaches a magnetic memory device including each of a magnetoresistance effect element 31, a switching element (selector) 32, and a resistance element 33, in series, between first 10 and second 20 wiring layers (Iwayama: Figs. 1 and 2; abstract; ¶¶ 25-29). Iwayama further teaches that the resistance element 33 is a pn junction diode made from p- and n-doped layers of polysilicon 33a, 33b (Iwayama: ¶¶ 42-47; Fig. 6). Iwayama explains the benefit of the pn-junction diode as the resistance element 33 as follows:
[0047] As described above, the memory cell 30 of this embodiment has the configuration in which the magnetoresistance effect element 31, selector 32, and resistance element 33 are connected in series. By virtue of such a configuration, in this embodiment, it is possible to obtain a magnetic memory device capable of suppression of read disturb and reduction in power consumption and capable of carrying out an appropriate read operation. …
(Iwayama: ¶ 47; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the pn-junction diode resistance element 33 made of p-doped and n-doped polysilicon (Iwayama: ¶ 43), as the resistance element 17 in Igarashi, in order to, in addition to the resistance function, “obtain a magnetic memory device capable of suppression of read disturb and reduction in power consumption and capable of carrying out an appropriate read operation” (id.), as taught by Iwayama. As such, Iwayama may be seen as an improvement to Igarashi in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 1 and 12.
With regard to claims 2, 6, 8, 9, and 11, Igarashi further discloses,
2. (Original) The memory device of claim 1, wherein the magnetoresistance effect element 14/15/11/12/13 is provided on an upper layer side of the switching element 2.
6. (Original) The memory device of claim 1, wherein the resistive layer 17A is formed of a semiconductor material [¶¶ 141-145, noting that the transition metal oxides and lanthanoid oxides are termed band-gap materials (¶ 145) indicating that they may be taken as semiconductor materials].
8. (Original) The memory device of claim 1, wherein the magnetoresistance effect element 14/15/11/12/13 includes:
[1] a first magnetic layer 13 having a variable magnetization direction [¶ 78];
[2] a second magnetic layer 11 having a fixed magnetization direction [¶ 78]; and
[3] a nonmagnetic layer 12 [¶ 79] provided between the first magnetic layer 13 and the second magnetic layer 11.
9. (Original) The memory device of claim 8, wherein
[1] the magnetoresistance effect element 14/15/11/12/13 further includes a third magnetic layer 14 [¶ 84],
[2] the second magnetic layer 11 is provided between the nonmagnetic layer 12 and the third magnetic layer 14, and
[3] the second magnetic layer 11 and the third magnetic layer 14 are antiferromagnetically coupled to each other [¶ 84: “The shift cancellation layer 14 is anti-ferromagnetically bonded to the reference layer 11 via the non-magnetic layer 15. Accordingly, the stack including the reference layer 11 and the shift cancellation layer 14 forms a synthetic anti-ferromagnetic (SAF) structure.”].
11. (Original) The memory device of claim 1, wherein the switching element 2 [¶¶ 64-70] is a two-terminal type switching element [¶ 65], and has a characteristic of changing from an off state to an on state when a voltage applied between two terminals thereof is higher than a threshold voltage [¶¶ 42 : “the switching element 2 is turned on (changes to a low resistive state, where it is electrically conductive) when a voltage equal to or higher than the threshold voltage of the switching element 2 is applied between the two terminals of the switching element 2.”].
The embodiments shown in each of Figs. 8(a) and 11 of Igarashi—viewed upside down— and modified according to Iwayama to make the resistive layer 80 of Igarashi (infra) from the p- and n-doped polysilicon junction diode (supra), teaches all of the limitations of claims 1 and 3-5, as follows:
1. (Currently Amended) A memory device comprising:
[1] a first wiring line 51 extending along a first direction X [¶ 49; Fig. 3];
[2] a second wiring line 50 [¶ 49; Fig. 3] provided on an upper layer side of the first wiring line 51 and extending along a second direction Y intersecting the first direction X; and
[3a] a memory cell MC [¶ 51; Fig. 3] provided between the first wiring line 51 and the second wiring line 50, and including
[3b] a magnetoresistance effect element 13/12/11/15/14 [¶¶ 71-84; Figs. 6, 9], a switching element 2 [¶¶ 64-70], a middle electrode 19A [¶¶ 83, 85-86] provided between the magnetoresistance effect element 13/12/11/15/14 and the switching element 2, and
[3c] and a resistive layer 80 [Fig. 8(a); ¶ 121], 60 [Fig. 11; ¶ 165] provided between the magnetoresistance effect element 13/12/11/15/14 and the second wiring line 50,
[3d] wherein a resistance of the resistive layer 80, 60 is higher than a resistance of the middle electrode 19A [because 19A is conductive, while 80 and 60 are resistors], and
[3e] the resistive layer 80, 60 is formed of a semiconductor material containing silicon (Si), germanium (Ge) or carbon (C) [as taught by Iwayama (supra)].
3. (Original) The memory device of claim 1, wherein the magnetoresistance effect element 13/12/11/15/14 is provided on a lower layer side of the switching element 2.
4. (Original) The memory device of claim 3, wherein the resistive layer 80 is provided on an upper layer side of the switching element 2 [Fig. 8(a)].
5. (Original) The memory device of claim 3, wherein the resistive layer 60 is provided on a lower layer side of the switching element 2 [Fig. 11].
B. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi in view of Iwayama, as applied to claim 1 above, and further in view of US 2021/0257413 (“Kanaya”).
Claim 7 reads,
7. (Original) The memory device of claim 1, wherein the middle electrode is formed of a material containing titanium (Ti) and nitrogen (N), a material containing tungsten (W) and nitrogen (N), or a material containing tantalum (Ta) and nitrogen (N).
The prior art of Igarashi in view of Iwayama, as explained above, teaches each of the features of claim 1.
Igarashi does not give the composition of the electrodes 19A, 19B of the magnetoresistance element, electrode 19A being the claimed “middle electrode”. Igarashi states that the electrodes, 19A and 19B, are “conductive layers” (Igarashi: ¶ 83).
Kanaya, like Igarashi, teaches a memory device including an array of magnetoresistance memory elements 40 (Kanaya: Figs. 1-2; ¶¶ 32-37) including a MTJ and a two-terminal selector or switch 20/50/70, the MTJ (Kanaya: Figs. 3-4; ¶¶ 39-42) having lower 62 and upper 64 electrodes and the two-terminal selector or switch having lower 20 and upper 70 electrodes (Kanaya: Figs. 3-4; ¶ 42). Kanaya further teaches that the lower 62 and upper 64 electrodes of the MTJ, the lower electrode 62 being equivalent to the claimed “middle electrode”, as in Igarashi, may be made of each made of “tungsten nitride (WN), tantalum nitride (TaN) , and titanium nitride (TiN)” (Kanaya: ¶¶ 43, 44).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the upper 19B and lower 19A electrodes of the MTJ in Igarashi from TiN, TaN, or WN because Igarashi is merely silent as to the material, such that one having ordinary skill in the art would use known materials for the identical purpose of forming the lower and upper electrodes of an MTJ, wherein the lower electrode may interface an electrode of a two-terminal switch for accessing said MTJ, such as the electrode materials taught in Kanaya. As such, the selection of TiN, TaN, or WN amounts to obvious material choice, as evidenced by Kanaya. (See MPEP 2144.07.)
C. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi in view of Iwayama, as applied to claims 1 and 8, above, and further in view of US 2021/0184102 (“Lee”).
Claim 10 reads,
10. (Original) The memory device of claim 8, wherein
[1] the magnetoresistance effect element further includes an auxiliary layer that enhances a perpendicular magnetic anisotropy of the first magnetic layer, and
[2] the first magnetic layer is provided between the nonmagnetic layer and the auxiliary layer.
The prior art of Igarashi in view of Iwayama, as explained above, teaches each of the features of claims 1 and 8.
Igarashi does not disclose the claimed auxiliary layer.
First Lee and Igarashi share at least one common inventor, i.e. Taiga ISODA. Lee, like Igarashi, teaches a memory device including an MTJ 100 including a variable or storage magnetic layer, i.e. the “free layer 107 having a variable magnetization direction” (¶ 42) on a barrier layer 106, in turn on a SAF including a pinned layer 104, spacer layer 103, and “shift cancelling layer 102” (Lee: ¶ 54), equivalent to the “shift cancelling layer 14” in Igarashi (Igarashi: ¶¶ 84-85). Lee further adds a “thermal stability enhanced layer (TSEL) 108” (Lee: ¶ 60) directly contacting the variable or storage magnetic layer 107, “to enhance the thermal stability (Δ) and the perpendicular magnetic anisotropy field (Hk) of the free layer 107” (Lee: ¶ 94; emphasis added). The “TSEL 108 may include an alloy based on Fe, O and X, for example, an Fe—O—X alloy, wherein X may include Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Ir, Mg, Sr, Ba, or a combination thereof” (Lee: ¶ 61).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the TSEL layer 108 of Lee in the MTJ of Igarashi directly on and contacting the variable or storage magnetic layer 13 of Igarashi, in order to “enhance the thermal stability (Δ) and the perpendicular magnetic anisotropy field (Hk) of the free layer” (Lee: ¶ 94) of Igarashi, as taught in Lee (Lee: ¶ 94, supra). As such, Lee may be seen as an improvement to Igarashi, in this aspect. (See MPEP 2143.)
III. Response to Arguments
Applicant’s arguments filed 08/12/2026 have been fully considered but they are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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