DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Response to Arguments
In response to applicant’s arguments that the species restriction lacks search burden examiner politely finds this unpersuasive. Due to the nature of an independent or distinct species restriction there is a search burden due to at least one of the following facture.
(a) the inventions, species, or groupings have acquired a separate status in the art in view of their different classification;
(b) the inventions, species, or groupings have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions, species, or groupings require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search quires);
(d) the prior art applicable to one invention would not likely be applicable to another invention; and
(e) the inventions, species, or groupings are likely to raise different non prior art issues under 35 U.S.C. 101 and/or 35.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimihiro Satoh et al. (US 20090251973 A1) hereinafter referred to as “Satoh”.
Regarding Claim 1 Satoh teaches
An integrated circuit device (Fig 13 and/or Fig 11) comprising:
a source line (201) extending in a first horizontal direction on a substrate (200);
a channel layer(203) extending in a vertical direction perpendicular to a top surface of the substrate(200), the channel layer (203) being on (Fig13) the source line (201) and having a first sidewall (right) and a second sidewall(left);
a trapping layer (211 and 210) on the first sidewall (right) of the channel layer and comprising an oxide semiconductor(210 Para [0051]);
a word line (213) on at least one sidewall of the trapping layer and extending in a second horizontal direction (into the page) crossing the first horizontal direction;
a gate insulation layer (212) between the at least one sidewall of the trapping layer and the word line(212 is in between 213 and 211 with 210); and
a bit line (217) electrically connected to the channel layer and extending ([0044][0038]) in the first horizontal direction,
wherein the channel layer has a first bandgap energy (every material has a band gap energy), and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.
The relative bandgap energies of the trapping layer and the channel layer are result-effective variables in charge-trapping memory design since they affect carrier confinement, leakage, and retention. Since Satoh already teaches a channel layer 203 and a nitride trapping layer 211, it would have been obvious to select materials such that the trapping layer has a greater bandgap energy than the channel layer in order to obtain predictable improvements in charge retention.
Regarding Claim 2 Satoh teaches
The integrated circuit device of claim 1,
wherein a valence band offset between a valence band level of the channel layer and a valence band level of the trapping layer is 0.5 eV or greater.
Satoh teaches that the nitride layer functions as the charge storage region and that the channel and nitride cooperate to store charge for memory operation.
Although Satoh does not expressly quantify the valence band offset,
It would have been obvious to a person of ordinary skill in the art to configure the trapping layer and channel materials such that the valence band offset is at least 0.5 eV, because a sufficiently large valence band offset is a predictable design parameter used to improve hole confinement, reduce charge leakage, and enhance retention in charge-trapping memory devices. Selecting materials to achieve a minimum offset of 0.5 eV would have constituted routine optimization of a result-effective variable in a known MONOS structure. A larger valence band offset improves trapping performance and retention, reinforcing that the claimed offset is an expected material-property choice rather than a non-obvious structural distinction
Regarding Claim 3 Satoh Teaches
The integrated circuit device of claim 1,
wherein a valence band offset between a valence band level of the channel layer and a valence band level of the trapping layer is greater than a conduction band offset between a conduction band level of the channel layer and a conduction band level of the trapping layer.
A person of ordinary skill in the art would have understood that, in charge-trapping memory structures, it is desirable for the trapping layer to present a greater barrier to carrier escape than to carrier injection, which is achieved by designing the valence band offset to be greater than the conduction band offset. This is because the storage layer must retain trapped charge while still permitting programming and erasing under applied bias conditions. Accordingly, it would have been obvious to select the materials of the channel and trapping layers so that the valence band offset exceeds the conduction band offset, as this represents a known and predictable approach to improving retention and memory-window performance in MONOS devices. the trapping layer selected to have a larger bandgap and favorable band alignment relative to the channel layer, further supports that the claimed relationship would have been an obvious design choice.
Regarding Claim 5 Satoh teaches
The integrated circuit device of claim 1,
wherein a source region (202 Fig 13) is between the channel layer (203) and the source line (201), and a drain region (Fig 11 element 108) is between the channel layer (103 which is mapped to 203) and the bit line (217).
Regarding Claim 7 Satoh teaches
The integrated circuit device of claim 5,
further comprising: a mold insulation layer (Fig 13 element 209 and or a portion of 210) covering the second sidewall (left) of the channel layer and the source line(201), wherein the trapping layer (211 and 210) comprises a vertical extension and a horizontal extension, the vertical extension of the trapping layer contacts the first sidewall (right) of the channel layer, and the horizontal extension of the trapping layer is on (above) the source region.(202)
Regarding Claim 8 Satoh teaches
The integrated circuit device of claim 1,
wherein the word line (213), the gate insulation layer (212), and the trapping layer (211 with at least a portion of 210) each have an L-shaped vertical cross-sectional shape. (Fig. 13)
Regarding Claim 9 Satoh teaches
The integrated circuit device of claim 1,
Satoh further teaches a voltage arrangement that is opposite to that of the program voltage and therefore teaches
wherein, when a program voltage having a negative value is applied to the word line, the integrated circuit device is configured to allow the trapping layer to trap holes from the channel layer, and, when an erase voltage having a positive value is applied to the word line, the integrated circuit device is configured to allow electrons to move from the channel layer to recombine with holes trapped in the trapping layer.(Para [0037])
Regarding Claim 10 Satoh teaches
The integrated circuit device of claim 1,
Satoh teaches a metal oxide nitride oxide silicon (MONOS) non-volatile memory that can be interpreted
wherein the integrated circuit device includes a capacitor-less dynamic random-access memory (DRAM) device. (Since the MONOS memory does not use a capacitor)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh as applied to Claim 1 further in view of Seongjae Cho et al. (US 10714479 B2) hereinafter referred to as “Cho” and further in view of Gurtej S Sandhu et al. (US 9112046 B2) hereinafter referred to as “Sandhu”.
Regarding Claim 4 Satoh teaches
The integrated circuit device of claim 1,
Satoh does not teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material,
Cho does teach a polysilicon channel in DRAM device and does teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material, (Cho Col 1 lines 55-62)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh such that the channel layer comprises polysilicon, as described in Cho because the modification allows for a dramatic improvement in the retention time of the stored holes. (Cho Col 1 lines 55-62)
Satoh in view of Cho does not teach
the trapping layer comprises at least one of indium gallium zinc oxide (In.GayZn2O), indium tungsten oxide (In.WyO), indium tin gallium oxide (In.SnyGa2O), indium aluminum zinc oxide (In.AlyZn2O), indium gallium oxide (In.GayO), indium tin zinc oxide (In.SnyZn2O), indium gallium silicon oxide (In.GaySi2O), indium zinc oxide (In.ZnyO), indium oxide (In"O), magnesium aluminum zinc oxide (Mg.AlyZn2O), zinc tin oxide (Zn.SnyO), zirconium zinc tin oxide (Zr.ZnySn2O), gallium zinc tin oxide (Ga.ZnySn2O), aluminum zinc tin oxide (AlxZnySn2O), or tin oxide (SnXO).
Sandhu does teach a memory device with a trapping material of Gallium indium zinc oxide and is relied upon to teach
the trapping layer comprises at least one of indium gallium zinc oxide (In.GayZn2O), indium tungsten oxide (In.WyO), indium tin gallium oxide (In.SnyGa2O), indium aluminum zinc oxide (In.AlyZn2O), indium gallium oxide (In.GayO), indium tin zinc oxide (In.SnyZn2O), indium gallium silicon oxide (In.GaySi2O), indium zinc oxide (In.ZnyO), indium oxide (In"O), magnesium aluminum zinc oxide (Mg.AlyZn2O), zinc tin oxide (Zn.SnyO), zirconium zinc tin oxide (Zr.ZnySn2O), gallium zinc tin oxide (Ga.ZnySn2O), aluminum zinc tin oxide (AlxZnySn2O), or tin oxide (SnXO). (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh in view of Cho such that the trapping layer comprises indium gallium zinc oxide, as described in Sandhu because the modification allows for the fabrication with a relatively low temperature (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31).
Claim(s) 6, 11-13, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Satoru Ohshita et al. (US 20220344334 A1) hereinafter referred to as “Ohshita”.
Regarding Claim 6 Satoh teaches
The integrated circuit device of claim 5,
Satoh does not teach the material for the source and drain region
wherein the source region and the drain region comprise polysilicon doped with a p-type impurity, silicon germanium doped with a p-type impurity, or a 2-dimensional material doped with a p-type impurity.
Ohshita does further teach the material
wherein the source region and the drain region (314a and 314b) comprise polysilicon doped with a p-type impurity, silicon germanium doped with a p-type impurity (Para [0190], [0191], [0187]) , or a 2-dimensional material doped with a p-type impurity.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh in view of Ohshita in view of Kato such that the source region and the drain region comprise silicon germanium doped with a p-type impurity, as described in Ohshita because the modification allows for the source and drain to be a low-resistance region. (Ohshita Para [0190], [0191], [0187])
Regarding claim 11 Satoh teaches
An integrated circuit device (Fig 13 and/or Fig 11) comprising:
a source line (201) extending in a first horizontal direction on a substrate (200);
a source region (202 Fig 13) on the source line;
a channel layer (203) extending from the source region in a vertical direction perpendicular to a top surface of the substrate (200), the channel layer (203) having a first sidewall (right) and a second sidewall (left) facing each other;
a trapping layer (211 and 210)on the first sidewall (right) of the channel layer and on a top surface of the source region, the trapping layer comprising an oxide semiconductor (210 Para [0051]);
a word line (213) on the first sidewall (right) of the channel layer and on the top surface of the source region, the trapping layer and a gate insulation layer(212) being between the channel layer and the word line and between the source region and the word line;
a drain region (Fig 11 element 108) on a top surface of the channel layer (103 which is mapped to 203); and a bit line (217) electrically connected to the drain region and extending in the first horizontal direction (Fig 11 and 13, Para [0044][0038])
Satoh does not explicitly teach
wherein a valence band offset between a valence band level of the channel layer and a valence band level of the trapping layer is 0.5 eV or greater.
Satoh teaches that the nitride layer functions as the charge storage region and that the channel and nitride cooperate to store charge for memory operation.
Although Satoh does not expressly quantify the valence band offset,
It would have been obvious to a person of ordinary skill in the art to configure the trapping layer and channel materials such that the valence band offset is at least 0.5 eV, because a sufficiently large valence band offset is a predictable design parameter used to improve hole confinement, reduce charge leakage, and enhance retention in charge-trapping memory devices. Selecting materials to achieve a minimum offset of 0.5 eV would have constituted routine optimization of a result-effective variable in a known MONOS structure. A larger valence band offset improves trapping performance and retention, reinforcing that the claimed offset is an expected material-property choice rather than a non-obvious structural distinction
Satoh does not teach
a source region comprising a p-type impurity;
the drain region comprising a p-type impurity
Ohshita does further teach the material to be silicon germanium doped with a p-type impurity and is therefore relied upon to teach
a source region (314a and or 314b) comprising a p-type impurity;
the drain region (314a and or 314b) comprising a p-type impurity; (Para [0190], [0191], [0187])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh such that the source region and the drain region comprise silicon germanium doped with a p-type impurity, as described in Ohshita because the modification allows for the source and drain to be a low-resistance region. (Ohshita Para [0190], [0191], [0187])
Regarding claim 12 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
Satoh further teaches
wherein the channel layer has a first bandgap energy (every material has a band gap energy), and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.
The relative bandgap energies of the trapping layer and the channel layer are result-effective variables in charge-trapping memory design since they affect carrier confinement, leakage, and retention. Since Satoh already teaches a channel layer 203 and a nitride trapping layer 211, it would have been obvious to select materials such that the trapping layer has a greater bandgap energy than the channel layer in order to obtain predictable improvements in charge retention.
Regarding claim 13 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
wherein a valence band offset between a valence band level of the channel layer and a valence band level of the trapping layer is greater than a conduction band offset between a conduction band level of the channel layer and a conduction band level of the trapping layer.
A person of ordinary skill in the art would have understood that, in charge-trapping memory structures, it is desirable for the trapping layer to present a greater barrier to carrier escape than to carrier injection, which is achieved by designing the valence band offset to be greater than the conduction band offset. This is because the storage layer must retain trapped charge while still permitting programming and erasing under applied bias conditions. Accordingly, it would have been obvious to select the materials of the channel and trapping layers so that the valence band offset exceeds the conduction band offset, as this represents a known and predictable approach to improving retention and memory-window performance in MONOS devices. the trapping layer selected to have a larger bandgap and favorable band alignment relative to the channel layer, further supports that the claimed relationship would have been an obvious design choice.
Regarding claim 15 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
Satoh further teaches
further comprising: a mold insulation layer (Fig 13 element 209 and or a portion of 210) covering the second sidewall (left) of the channel layer and of the source line(201), wherein the trapping layer (211 and 210) comprises a vertical extension and a horizontal extension, the vertical extension of the trapping layer contacts the first sidewall (right) of the channel layer, and the horizontal extension of the trapping layer is on (above) the source region.(202)
Regarding claim 16 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
Satoh further teaches
wherein the word line (213), the gate insulation layer(212), and the trapping layer (211 with at least a portion of 210) each have an L-shaped vertical cross-sectional shape. (Fig. 13)
Regarding claim 17 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
Satoh further teaches a voltage arrangement that is opposite to that of the program voltage and therefore teaches
wherein, when a program voltage having a negative value is applied to the word line, the integrated circuit device is configured to allow the trapping layer to trap holes from the channel layer, and, when an erase voltage having a positive value is applied to the word line, the integrated circuit device is configured to allow electrons to move from the channel layer to recombine with holes trapped in the trapping layer.(Para [0037])
and Satoh teaches a metal oxide nitride oxide silicon (MONOS) non-volatile memory that can be interpreted
and the integrated circuit device includes a capacitor-less dynamic random- access memory (DRAM) device. (Since the MONOS memory does not use a capacitor)
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Ohshita as applied to Claim 11 further in view of Seongjae Cho et al. (US 10714479 B2) hereinafter referred to as “Cho” and further in view of Gurtej S Sandhu et al. (US 9112046 B2) hereinafter referred to as “Sandhu”.
Regarding claim 14 Satoh in view of Ohshita teaches
The integrated circuit device of claim 11,
Satoh does not teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material,
Cho does teach a polysilicon channel in DRAM device and does teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material, (Cho Col 1 lines 55-62)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh such that the channel layer comprises polysilicon, as described in Cho because the modification allows for a dramatic improvement in the retention time of the stored holes. (Cho Col 1 lines 55-62)
Satoh in view of Cho does not teach
and the trapping layer comprises at least one of indium gallium zinc oxide (InxGayZn2O), indium tungsten oxide (InxWyO), indium tin gallium oxide (InXSnyGa2O), indium aluminum zinc oxide (InXAlyZn2O), indium gallium oxide (InXGayO), indium tin zinc oxide (InXSnyZn2O), indium gallium silicon oxide (InXGaySi2O), indium zinc oxide (InXZnyO), indium oxide (InxO), magnesium aluminum zinc oxide (MgxAlyZn2O), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide (ZrxZnySn2O), gallium zinc tin oxide (Ga ZnySn2O), aluminum zinc tin oxide (A1XZnySn2O), or tin oxide (SnXO).
Sandhu does teach a memory device with a trapping material of Gallium indium zinc oxide and is relied upon to teach
the trapping layer comprises at least one of indium gallium zinc oxide (In.GayZn2O), indium tungsten oxide (In.WyO), indium tin gallium oxide (In.SnyGa2O), indium aluminum zinc oxide (In.AlyZn2O), indium gallium oxide (In.GayO), indium tin zinc oxide (In.SnyZn2O), indium gallium silicon oxide (In.GaySi2O), indium zinc oxide (In.ZnyO), indium oxide (In"O), magnesium aluminum zinc oxide (Mg.AlyZn2O), zinc tin oxide (Zn.SnyO), zirconium zinc tin oxide (Zr.ZnySn2O), gallium zinc tin oxide (Ga.ZnySn2O), aluminum zinc tin oxide (AlxZnySn2O), or tin oxide (SnXO). (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh in view of Cho such that the trapping layer comprises indium gallium zinc oxide, as described in Sandhu because the modification allows for the fabrication with a relatively low temperature (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Satoh in view of Satoru Ohshita et al. (US 20220344334 A1) hereinafter referred to as “Ohshita”, Seongjae Cho et al. (US 10714479 B2) hereinafter referred to as “Cho” and further in view of Gurtej S Sandhu et al. (US 9112046 B2) hereinafter referred to as “Sandhu”.
Regarding Claim 18 Satoh teaches
An integrated circuit device (Fig 13 and/or Fig 11) comprising:
a source line (201) extending in a first horizontal direction on a substrate(200);
a mold insulation layer (Fig 13 element 209 and a portion of 210) on the substrate to cover the source line and having an opening;
a source region (202 Fig 13) in the opening (between) of the mold insulation layer, the source region being on a top surface of the source line(201);
a channel layer (203) in the opening (between) of the mold insulation layer, the channel layer extending from the source region in a vertical direction perpendicular to a top surface of the substrate (Fig 13), the channel layer having a first sidewall and a second sidewall facing each other, the second sidewall being in contact with the mold insulation layer;(in the middle both side walls of 203 touch the mold insulation layer of 209 with at least a portion of 210).
a trapping layer(211 and at least a portion of 210) in the opening (between) of the mold insulation layer, the trapping layer being on the first sidewall of the channel layer (in the middle the trapping layer is on both sides of 203) and on a top surface of the source region, the trapping layer comprising an oxide semiconductor(210);
a word line(213) in the opening of the mold insulation layer, the word line being on the first sidewall of the channel layer and on the top surface of the source region, the trapping layer(211 and 210) and a gate insulation layer (212) being between the channel layer(203) and the word line (213)and between the source region(202) and the word line(213);
a drain region (Fig 11 element 108)in the opening (between) of the mold insulation layer (Fig 13 element 209 and a portion of 210), the drain region being on a top surface of the channel layer; and
a bit line (217) electrically connected to the drain region and extending in the first horizontal direction,(Fig 11 and 13, Para [0044][0038])
Satoh does not teach
the source region comprising a p-type impurity
the drain region comprising a p-type impurity
Ohshita does further teach the material to be silicon germanium doped with a p-type impurity and is therefore relied upon to teach
a source region (314a and or 314b) comprising a p-type impurity;
the drain region (314a and or 314b) comprising a p-type impurity; (Para [0190], [0191], [0187])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh such that the source region and the drain region comprise silicon germanium doped with a p-type impurity, as described in Ohshita because the modification allows for the source and drain to be a low-resistance region. (Ohshita Para [0190], [0191], [0187])
Satoh in view of Ohshita does not teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material, and
Cho does teach a polysilicon channel in DRAM device and does teach
wherein the channel layer comprises polysilicon, silicon germanium, or a 2- dimensional material, (Cho Col 1 lines 55-62)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh in view of Ohshita such that the channel layer comprises polysilicon, as described in Cho because the modification allows for a dramatic improvement in the retention time of the stored holes. (Cho Col 1 lines 55-62)
Satoh in view of Ohshita and Cho does not teach
the trapping layer comprises at least one of indium gallium zinc oxide (InXGayZn2O), indium tungsten oxide (InXWyO), indium tin gallium oxide (InxSnyGa2O), indium aluminum zinc oxide (InxAlyZn2O), indium gallium oxide (InXGayO), indium tin zinc oxide (InXSnyZn2O), indium gallium silicon oxide (InXGaySi2O), indium zinc oxide (InxZnyO), indium oxide (InxO), magnesium aluminum zinc oxide (MgxAlyZn2O), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide (ZrXZnySn2O), gallium zinc tin oxide (GaxZnySn2O), aluminum zinc tin oxide (A1XZnySn2O), or tin oxide (SnXO).
Sandhu does teach a memory device with a trapping material of Gallium indium zinc oxide and is relied upon to teach
the trapping layer comprises at least one of indium gallium zinc oxide (In.GayZn2O), indium tungsten oxide (In.WyO), indium tin gallium oxide (In.SnyGa2O), indium aluminum zinc oxide (In.AlyZn2O), indium gallium oxide (In.GayO), indium tin zinc oxide (In.SnyZn2O), indium gallium silicon oxide (In.GaySi2O), indium zinc oxide (In.ZnyO), indium oxide (In"O), magnesium aluminum zinc oxide (Mg.AlyZn2O), zinc tin oxide (Zn.SnyO), zirconium zinc tin oxide (Zr.ZnySn2O), gallium zinc tin oxide (Ga.ZnySn2O), aluminum zinc tin oxide (AlxZnySn2O), or tin oxide (SnXO). (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Satoh in view of Ohshita and Cho such that the trapping layer comprises indium gallium zinc oxide, as described in Sandhu because the modification allows for the fabrication with a relatively low temperature (Sandhu Col 1 lines 58-64 and Col 3 lines 22-31).
Regarding Claim 19 Satoh in view of Ohshita, Cho and Sandhu teaches
The integrated circuit device of claim 18,
wherein a valence band offset between a valence band level of the channel layer and a valence band level of the trapping layer is greater than a conduction band offset between a conduction band level of the channel layer and a conduction band level of the trapping layer,
A person of ordinary skill in the art would have understood that, in charge-trapping memory structures, it is desirable for the trapping layer to present a greater barrier to carrier escape than to carrier injection, which is achieved by designing the valence band offset to be greater than the conduction band offset. This is because the storage layer must retain trapped charge while still permitting programming and erasing under applied bias conditions. Accordingly, it would have been obvious to select the materials of the channel and trapping layers so that the valence band offset exceeds the conduction band offset, as this represents a known and predictable approach to improving retention and memory-window performance in MONOS devices. the trapping layer selected to have a larger bandgap and favorable band alignment relative to the channel layer, further supports that the claimed relationship would have been an obvious design choice.
and the valence band offset is 0.5 eV or greater.
Satoh teaches that the nitride layer functions as the charge storage region and that the channel and nitride cooperate to store charge for memory operation.
Although Satoh does not expressly quantify the valence band offset,
it would have been obvious to a person of ordinary skill in the art to configure the trapping layer and channel materials such that the valence band offset is at least 0.5 eV, because a sufficiently large valence band offset is a predictable design parameter used to improve hole confinement, reduce charge leakage, and enhance retention in charge-trapping memory devices. Selecting materials to achieve a minimum offset of 0.5 eV would have constituted routine optimization of a result-effective variable in a known MONOS structure. A larger valence band offset improves trapping performance and retention, reinforcing that the claimed offset is an expected material-property choice rather than a non-obvious structural distinction.
Regarding Claim 20 Satoh in view of Ohshita, Cho, and Sandhu teaches
The integrated circuit device of claim 18,
Satoh further teaches
wherein the trapping layer (211 and at least a portion of 210) comprises a vertical extension and a horizontal extension, the vertical extension of the trapping layer contacts the first sidewall of the channel layer (Fig 13), the horizontal extension of the trapping layer is on the source region (Fig 13), and the word line (213), the gate insulation layer(212), and the trapping layer(211 with at least a portion of 210) each have an L-shaped vertical cross-sectional shape.(Fig 13)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bhattacharyya, Arup (US-20040041206-A1), OUYANG; Yingjie (US-20210066335-A1), Rabkin; Peter (US-9449985-B1), Kiyoshi Kato et al. (US 9443592 B2) (Kato may be relied upon to teach a trapping layer bandgap energy), Satoru Ohshita et al. (US 20220344334 A1) (Ohshita may be relied upon further to teach and Channel layer bandgap energy).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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