DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US Pub. 2020/0294930 A1).
In re claim 1, Wang et al. discloses (figs. 1A-2G) a method of manufacturing a semiconductor package, comprising: disposing a first die (fig. 2A; D1) on a carrier (102), wherein the first die has a top surface and a bottom surface opposing to the top surface; forming a plurality of first conductive bumps (AM1, D1d) on the top surface of the first die through a wire bonding process, wherein the first conductive bumps are electrically connected to the first die; forming a molding layer (fig. 1B & 2B; D1e, 110) to cover the first conductive bumps and the first die; grinding the molding layer (fig. 2C; to expose the first conductive bumps; forming a redistribution layer (fig. 2D; 112a) on the molding layer to electrically connect to the first conductive bumps; and removing the carrier (fig. 2E).
In re claim 2, Wang et al. discloses (figs. 1A-2G) further comprising: disposing a second die (another D1, right side) on the carrier; forming a plurality of second conductive bumps (fig. 2C; AM1-TS, D1d-TS) on the second die through a wire bonding process, wherein the second conductive bumps are electrically connected to the second die; covering the second conductive bumps and the second die with the molding layer (110); exposing the second conductive bumps from the molding layer (fig. 2C; 110’); and electrically connecting the redistribution layer to the second conductive bumps (fig. 2D).
In re claim 3, Wang et al. discloses [0022] the first conductive bumps are formed with one of gold wires, copper wires and alloy wires.
In re claim 4, Wang et al. discloses (figs. 1A-2G) the molding layer (110) has a bottom surface that is flush with the bottom surface of the first die (D1).
In re claim 5, Wang et al. discloses (figs. 1A-2G) after forming the redistribution layer, disposing a plurality of solder balls (fig. 2D; 114) on the redistribution layer, wherein the solder balls are electrically connected to the redistribution layer.
In re claim 6 Wang et al. discloses (figs. 1A-2G) wherein the first die and the second die are disposed side by side on the carrier.
In re claim 7, Wang et al. shows (fig. 2D) a semiconductor package, comprising: a first die (D1) having a top surface and a bottom surface opposing to the top surface; a plurality of first bonding pads (D1b) disposed on the top surface of the first die; a plurality of first conductive bumps (AM1, D1d) disposed on the first bonding pads respectively, wherein the first conductive bumps are electrically connected to the first die; a molding layer (110’) covering the top surface of the first die and exposing the first conductive bumps; and a redistribution layer (112a) disposed on the molding layer to electrically connect to the first conductive bumps.
In re claim 8, Wang et al. shows (fig. 2D) a second die (another of the D1, right sided) having opposing top and bottom surfaces; a plurality of second bonding pads (D1b) disposed on the top surface of the second die; and a plurality of second conductive bumps (D1d) disposed on the second bonding pads respectively, wherein the second conductive bumps are electrically connected to the second die; wherein the molding layer (110’) further covers the top surface of the second die and exposes the second conductive bumps; and the redistribution layer (112a) is further electrically connected to the second conductive bumps.
In re claim 9, Wang et al. shows (fig. 2D) wherein the molding layer (110’)has a bottom surface that is flush with the bottom surface of the first die.
In re claim 10, Wang et al. shows (fig. 2D)a plurality of solder balls (114) disposed on the redistribution layer, the solder balls being electrically connected to the redistribution layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hung (US 8,928,117 B1), Fujishima (US Pub. 2023/0207434 A1), Kim (US Pub. 2023/0133322 A1), Lee (US Pub. 2022/0415838 A1), Chang (US Pub. 2019/0378803 A1), Lee (WO-2017095094 A1), Lin (DE-102012109484 A1), and CN-105514099-A) also disclose various elements of the claims. Each of these references disclose most of the elements of the claims and would also serve as base references in 35 USC 102 or 103 Rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2817
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