Prosecution Insights
Last updated: October 02, 2026
Application No. 18/606,421

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Mar 15, 2024
Priority
Sep 30, 2021 — provisional 63/261,847 +1 more
Examiner
WARREN, MATTHEW E
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Socionext Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
892 granted / 1017 resolved
+19.7% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
18 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
35.1%
-4.9% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1017 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takeno et al. (WO 2021079511 A1). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. In re claim 1, Takeno et al. shows (fig. 21) a semiconductor device comprising: a substrate (11) including a first surface (at 4150) and a second surface (at 2120) opposite to the first surface; a first power supply line (3140) provided on the first surface; a first ground line (3150) provided on the first surface; a first area including the first power supply line and the first ground line (left side); a second power supply line (another of 3150) provided on the first surface; a second ground line (another 3140) provided on the first surface; a third power supply line (2150) provided on the second surface; a fourth power supply line (2120) provided on the second surface; a via (2151) provided in the substrate, to electrically connect the second power supply line (another of the 3150) and the third power supply line (2150); a second area including the second power supply line and the second ground line (right side); a third area (middle section) positioned between the first area and the second area in plan view; and a first power switch circuit including a first switch transistor (600P) electrically connected between the third power supply line and the fourth power supply line, the first switch transistor being provided on the second surface side of the substrate. In re claim 2, Takeno et al. shows (fig. 21) a first interconnect (4152) connected to the second power supply line. In re claim 3, Takeno et al. shows (fig. 21) wherein the second power supply line extends in a first direction in the second area. In re claims 4 and 5, Takeno et al. shows (fig. 21) wherein the first power switch circuit is provided in the second area in plan view or is provided in the third area in plan view (since the power switch circuits are provide across these areas. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6-10 are rejected under 35 U.S.C. 103 as being obvious over Takeno et al. (WO 2021079511 A1) in view of the cited case law. The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). In re claims 6 and 8-10, Takeno does not specifically disclose the additional power supply lines, switches, ground lines, vias and their configurations. It would have been obvious to one of ordinary skill in the art to use three, four, etc., power supply lines, switches, ground lines, and vias since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B). In re claim 7, Takeno shows all of the elements of the claims except wherein the arrangement spacing of a plurality of first ground lines in the second direction is different from arrangement spacing of a plurality of second ground lines in the second direction. It would have been obvious to one of ordinary skill in the art at the time the invention was made to form the ground lines having any desired spacing arrangement, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Schultz (US Pub. 2023/0096652 A1), Kim (US Pub. 2022/0130737 A1), Sio (US Pub. 2021/0118805 A1), Ding Shaofeng (KR-20220140279 A), and Cho (CN-113451256 A) also disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KRETELIA GRAHAM can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1017 resolved cases by this examiner. Grant probability derived from career allowance rate.

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