DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 5/13/26 have been fully considered but they are not persuasive.
Regarding the argument that Venkatesan does not disclose the cushioning material layer is configured to protect the port during formation of the groove in the encapsulation layer by laser etching: This is a purely functional limitation and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971);< In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). Further, laser etching grooves is a product-by-process limitation and "even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted). The structure is all claimed by Venkatesan and Chern so a prima facie case of obviousness has been made with respect to the laser etching and the function of protecting the port during laser etching. No structure has been added with this amendment.
Venkatesan teaches material at the port that form the cushioning material, so there must be some “protection” achieved since there is a block of material at the port. This covers the structure of the claim. The claim does not state an etch stop or protective layer.
Regarding the argument that Chern does not disclose a transparent cushioning material positioned between a chip sidewall and groove: In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Venkatesan is used to teach this limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan (US 11,686,906 B1) and Chern (US 2025/0062300 A1).
Venkatesan teaches:
1. A silicon photonic chip package module (Figs. 30C-D), comprising:
a silicon photonic chip (3002) having a top surface, a bottom surface and side surfaces (see Figs. 30C-D) and incorporating an optical signal processing element (3020), wherein a port (right end of each 3044) connected to the optical signal processing element (3020) is provided on one of the side surfaces (right);
an outer layer (not labeled) that surrounds the side surfaces of the chip (3002) (see Fig. 30D, the outer layer) and thus circumferentially surrounds the chip (3002);
a transparent cushioning material layer (SSCs) provided on said side surface of the silicon photonic chip (3002) so as to cover the port (right ends of 3044); and
wherein a groove (3050) for receiving a fiber optic therein is provided in the layer (see Fig. 3D, 3050 is within the overall footprint formed by the outer layer), the groove (3050) extending towards the port (ends of 3044) and one end of the groove terminating within the transparent cushioning material layer (SSCs) (see Fig. 3B), thereby allowing the port to be optically connected to the fiber optic (part of 350) through the transparent cushioning material (SSCs) layer and to receive an optical signal (C87 L37-55).
Venkatesan does not state that the cushioning material layer has the function of being configured to protect the port during formation of the groove in the encapsulation layer by laser etching. First, the method of forming the encapsulation layer by laser etching is a product by process limitation that does not add any structure and "even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted). The structure is all claimed by Venkatesan and Chern so a prima facie case of obviousness has been made with respect to the laser etching.
Venkatesan does not state the function of the cushioning material is for protecting the port during groove formation, but this is a purely functional limitation and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971);< In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). Again, all of the structure has been met so a prima facie case of obviousness has been established. Venkatesan teaches transparent cushioning material on the side surface of the chip to cover the port, so a person of ordinary skill the art would recognize the material is “protect” the port in some manner since there is material there just as claimed.
Venkatesan does not teach expressly a plastic encapsulation layer, which at least surrounds the side surfaces of the silicon photonic chip and thus at least circumferentially encapsulates the silicon photonic chip. Venkatesan shows the PIC having material surrounding each device (3020, 3030), the optics (3044, SSCs) and fiber optic cable mounting block (3050) (see Fig. 30D), but does not say it is a plastic encapsulation layer.
Chern teaches a silicon photonic chip package module (600, Figs. 6, 14) with an epoxy plastic encapsulation layer (318) that surrounds side surfaces of photonic chips (106) (P0047, 0067, 0083).
Venkatesan and Chern are analogous art because they are from the same field of endeavor, silicon photonic chip package modules.
At the time of the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the module of Venkatesan to have the outer layer surrounding the chip shown in Fig. 30D to be an epoxy plastic encapsulation layer as taught by Chern.
The motivation for doing so would have been to protect the chips while providing support for coupled optics (Chern, P0047, 0083).
Regarding claims 2-3: Venkatesan and Chern do not state wherein the transparent cushioning material layer has a light transmittance of 95% or higher or a thickness of 50-100 microns or the chips are spaced 50-100 microns from each other. Venkatesan does teach the cushioning material layer being spot size converters (SSCs). Spot size converters facilitate coupling signals through the PIC (C24 L30-35), therefore a person of ordinary skill the art at the time the invention was effectively filed to try having the cushioning material layer to have 95% plus light transmittance, since it has been held that “it is obvious to try - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success” is a rationale for arriving at a conclusion of obviousness. In re KSR International Co. v. Teleflex Inc. Again, Venkatesan teaches this layer being spot size converters, which are for signal coupling so near 100% light transmittance would be predicable and would succeed because there is no case for low transmittance this this layer.
Further, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to try a thickness of the spot size converters of Venkatesan of 50-100 microns, since it has been held that “it is obvious to try - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success” is a rationale for arriving at a conclusion of obviousness. In re KSR International Co. v. Teleflex Inc. Applicant’s own cushioning layer is also a spot size converter and therefore it would have been predictable for a person of ordinary skill in the art that the thickness of a spot size converter be in a range of known converters such as 50-100 microns.
Further, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to try having the chips spaced from each other 50-100 microns from each other, since it has been held that “it is obvious to try - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success” is a rationale for arriving at a conclusion of obviousness. In re KSR International Co. v. Teleflex Inc. Venkatesan show the chips being spaced from each other, yet four provided on the chip (see Fig. 30D), therefore it would have been predictable to try spacing the chips 50-100 microns from each other since this is consistent with known dimensions of these types of photonic package modules.
Further, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to try having the V-groove width be 10 microns to 1 mm, since it has been held that “it is obvious to try - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success” is a rationale for arriving at a conclusion of obviousness. In re KSR International Co. v. Teleflex Inc. Venkatesan the V-grooves housing optical fibers therefore one of ordinary skill the art would identify a groove width of 10 microns to 1 mm since this range would accommodate known fiber optics.
Venkatesan further teaches:
4. The silicon photonic chip package module of claim 1, wherein the transparent cushioning material layer (SSCs) has a height (part of 3058, so that height, see Fig. 30C) less than a height of the silicon photonic chip (3002) (see Fig. 30C, the height of the waveguide core layer is far less than the height of the overall chip).
5. The silicon photonic chip package module of claim 1, wherein the transparent cushioning material layer (SSCs) is configured as an optical element for modifying an optical signal from the fiber optic (spot size converting).
Regarding claim 6: Venkatesan and Chern do not state the spot size converters are is configured as an optical element in the form of a frustum of a cone, the frustum having a large base coupled to the side surface with the port provided therein, the frustum having a smaller base configured to be coupled to the fiber optic.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to try making the cushioning layer of Venkatesan and Chern in the shape of a frustum of a cone, the frustum having a large base coupled to the side surface with the port provided therein, the frustum having a smaller base configured to be coupled to the fiber optic, since it has been held that “it is obvious to try - choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success” is a rationale for arriving at a conclusion of obviousness. In re KSR International Co. v. Teleflex Inc. This shape described a spot size converter and Venkatesan teaches this layer is a spot size converter, so the claimed shape would have been predictable to use in Venkatesan with an expectation of success since a spot size converter is the exact component used as this layer.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan and Chern as applied to claim 1 above, and further in view of Yu et al (CN 110488434 A1) and the corresponding machine translation.
Venkatesan and Chern teach the silicon photonic chip package module previously discussed.
Venkatesan and Chern do not teach expressly:
7. The silicon photonic chip package module of claim 1, wherein: solder pads are provided on the top surface of the silicon photonic chip; the plastic encapsulation layer comprises: a first surface located on the same side of the silicon photonic chip package module as the top surface of the first surface and the silicon photonic chip; and a plurality of through holes, which extend through the plastic encapsulation layer in a direction of a thickness of the plastic encapsulation layer; and the silicon photonic chip package module further comprises a metal interconnect layer, which covers the first surface and part of the top surface and is electrically connected to the solder pads.
8. The silicon photonic chip package module of claim 1, further comprising first and second passivation layers for isolating the metal interconnect layer, the first passivation layer covering the first surface and the top surface and partially covered by the metal interconnect layer, the second passivation layer covering the metal interconnect layer and the first passivation layer.
9. The silicon photonic chip package module of claim 8, wherein first and second via holes are provided in the first passivation layer, and a conductive material is filled in the first and second via holes, one end of the conductive material filled in the first and second via holes electrically connected to the metal interconnect layer, the other end of the conductive material filled in the first and second via holes electrically connected to the conductive material filled in the through holes and the solder pads on the silicon photonic chip, thereby accomplishing electrical connection of the silicon photonic chip package module on the first surface, and wherein via holes are provided in the second passivation layer, and a conductive material is filled in the via holes to form a number of solder pads, one end of the solder pads are connected to the metal interconnect layer and the other end of the solder pads are exposed by the second passivation layer, thereby allowing the metal interconnect layer to be connected to an external circuit.
Yu teaches a silicon photonic chip package module (Figs. 1-3) wherein the module is the same disclosed by applicant. See the currently applicant’s drawings Figs. 1, 2 and 4 are the same as Yu Figs. 1-3 with the same reference numbers. Therefore, Yu clearly teaches : solder pads (at 500) are provided on the top surface of the silicon photonic chip (100); the plastic encapsulation layer comprises: a first surface located on the same side of the silicon photonic chip package module as the top surface of the first surface and the silicon photonic chip (see Fig. 3); and a plurality of through holes, which extend through the plastic encapsulation layer in a direction of a thickness of the plastic encapsulation layer (steps S6 and S7 in the translation); and the silicon photonic chip package module further comprises a metal interconnect layer (400), which covers the first surface and part of the top surface and is electrically connected to the solder pads (see Fig. 3);
first and second passivation layers (310, 320) for isolating the metal interconnect layer (400), the first passivation layer (310) covering the first surface and the top surface and partially covered by the metal interconnect layer (400), the second passivation layer (320) covering the metal interconnect layer (400) and the first passivation layer (310) (Fig. 3);
wherein first and second via holes are provided in the first passivation layer (310) (step S6 and S7), and a conductive material is filled in the first and second via holes (steps S6-S7), one end of the conductive material filled in the first and second via holes electrically connected to the metal interconnect layer (400), the other end of the conductive material filled in the first and second via holes electrically connected to the conductive material filled in the through holes and the solder pads on the silicon photonic chip (100), thereby accomplishing electrical connection of the silicon photonic chip package module on the first surface, and wherein via holes are provided in the second passivation layer (320), and a conductive material is filled in the via holes to form a number of solder pads, one end of the solder pads are connected to the metal interconnect layer (400) and the other end of the solder pads are exposed by the second passivation layer (320), thereby allowing the metal interconnect layer to be connected to an external circuit (see steps S6-S10).
Venkatesan, Chern and Yu are analogous art because they are from the same field of endeavor, photonic chip package modules.
At the time of the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the module taught by Venkatesan and Chern to use the solder pads, metal interconnector layers, passivation layers and via holes as taught by Yu.
The motivation for doing so would have been to reduce cost and complexity by using a known electrical chip layers already described by Yu.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached 9AM-6PM EST M-F.
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/RYAN A LEPISTO/Primary Examiner, Art Unit 2874
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