DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species 1 (figures 2/3), corresponding to claims 1-6, 8, 13-16, 19, and 20, in the reply filed on 4/29/26 is acknowledged. The traversal is on the ground(s) that there is no serious burden because there is “substantial overlap of core elements”. This is not found persuasive because even though there is overlap, there are also varying elements in each species that are identified as different embodiments, as noted in the restriction.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8, 13-16, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaran et al., US 2022/0189880, in view of Ishida et al., US 9,185,799.
Regarding claim 1, Pietambaran (figure 1) teaches a package substrate comprising:
a core substrate 114 including a first surface and a second surface opposite to the first surface;
a first core laminated structure 112-1 on the first surface of the core substrate 114, including a plurality of first core insulating layers 108 and a plurality of first cores wiring layers 116 on the plurality of first core insulating layers 108, and including a first chip mounting space (at 104) defined by the plurality of first core insulating layers 108;
a bridge chip 104 within the first chip mounting space (at 104) and including a bridge substrate 104 and a bridge pad (at 123); and
a second core laminated structure 112-2 on the second surface of the core substrate 114, and including a plurality of second core insulating layers 108 and a plurality of second core wiring layers 116 on the plurality of second core insulating layers 114.
Pietambaran fails to teach the plurality of first core insulating layers have a first coefficient of thermal expansion, and the plurality of second core insulating layers have a second coefficient of thermal expansion less than the first coefficient of thermal expansion.
Ishida (abstract) teaches the plurality of first core insulating layers 50A have a first coefficient of thermal expansion, and the plurality of second core insulating layers 50B have a second coefficient of thermal expansion less than the first coefficient of thermal expansion 50A.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the different coefficient of thermal expansions of Ishida in the invention of Pietambaran because Ishida teaches it prevents short circuiting (column 4, lines 34-40), prevents peeling (column 5, lines 3-7), controls warping (column 5, lines 18-37), and prevents connection failure (column 6, lines 3-16). Though Ishiba fails to each a bridge, Ishaba teaches the concept of compensating for the heat generated by a chip on one side of a substrate by choosing higher coefficient of thermal expansion insulating layers on the chip side. This concept applies to a bridge chip just as equally to an external chip.
With respect to claim 2, though Pietambaran (column 6, lines 3-15) fails to specifically teach a difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion is 5 ppm/oC or less, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the difference through routine experimentation (MPEP 2144.05).
As to claim 3, though Pietambaran, which teaches a resin insulation layer (column 8, lines 39-50), fails to teach each of the first core insulating layers and the second core insulating layers includes at least one of an Ajinomoto build-up film (ABF), benzocyclobutene (BCB), photo-imageable dielectric (PID), photosensitive polyimide (PSPI), solder resist, an epoxy molding compound (EMC), flame retardant 4 (FR-4), or bismaleimide triazine (BT), it would have been obvious to one of ordinary skill in the art at the time of the invention to replace the resin insulation layer in the invention of Pietambaran with these materials because they are known equivalent materials. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
In re claim 4, Pietambaran (see marked up figure 1 below) teaches the plurality of first core insulating layers 108 include, a lowermost core insulating layer 1 being closest to the first surface of the core substrate 114, from among the plurality of first core insulating layers 108, an uppermost core insulating layer 3 being farthest from the first surface of the core substrate 114, from among the plurality of first core insulating layers 108, and at least one middle core insulating layer 2 being between the lowermost core insulating layer 1 and the uppermost core insulating layer 3, from among the plurality of first core insulating layers 108, a side of the first chip mounting space (at 104) is surrounded by the uppermost core insulating layer 3, and the at least one middle core insulating layer 2 is exposed at a bottom of the first chip mounting space (at 104).
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Concerning claim 5, Pietambaran (figure 1) teaches the bridge pad (at 123) is on an upper surface of the bridge substrate 104, and the bridge chip 104 further includes, a bridge lower pad (at 122) on a lower surface of the bridge substrate 104, a bridge lower connection member 122 electrically connected to the bridge lower pad (at 122) and the first core wiring layers 116, and a bridge through-via 140 passing through the bridge substrate 104 to electrically connect the bridge lower pad (at 122) and the bridge pad (at 123) to each other.
Pertaining to claim 6, though Pietambaran teaches the bridge chip 104 is apart from the core substrate 114 in a first direction perpendicular to the first surface of the core substrate 114, and though Pietambaran fails to teach the first chip mounting space (at 104) is on a level corresponding to an upper portion of the first core laminated structure 112-1, it would have been obvious to one of ordinary skill in the art at the time of the invention for the first chip mounting space (at 104) is on a level corresponding to an upper portion of the first core laminated structure in the invention of Pietambaran because it is a conventionally known equivalent first chip mounting space location. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
In claim 8, Pietambaran (figure 1) teaches the bridge substrate 104 includes silicon (paragraph 0020 teaches 140 is a through-silicon via therefore 104 is made of silicon), the bridge chip 104 has a third coefficient of thermal expansion (silicon has a third coefficient of thermal expansion), and though Pietambaran fails to teach the third coefficient of thermal expansion is less than the first coefficient of thermal expansion, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative coefficient of thermal expansion through routine experimentation (MPEP 2144.05).
Regarding claim 13, Pietambaran (figure 1) teaches a package substrate comprising:
a core substrate114 including a first surface and a second surface opposite to the first surface;
a first core laminated structure 112-1 on the first surface of the core substrate 114, including a plurality of first core insulating layers 108, and including a plurality of first core wiring layers 116 forming an upper conductive path that is electrically connected to the core substrate 114;
a second core laminated structure 112-2 on the second surface of the core substrate 114, including a plurality of second core insulating layers 108, and including a plurality of second core wiring layers 116 forming a lower conductive path electrically connected to the core substrate 114; and
a bridge chip 104 in a first chip mounting space 9at 104) defined in an upper portion of the first core laminated structure 112-1 and including a bridge substrate 104 and a bridge pad (at 123), the bridge pad (at 123) electrically connected to the upper conductive path (through 122 & 123).
Pietambaran fails to teach a first insulating material having a first coefficient of thermal expansion and a second insulating material having a second coefficient of thermal expansion less than the first coefficient of thermal expansion.
Ishida (abstract) teaches the plurality of first core insulating layers 50A have a first coefficient of thermal expansion, and the plurality of second core insulating layers 50B have a second coefficient of thermal expansion less than the first coefficient of thermal expansion 50A. Though Ishiba fails to each a bridge, Ishaba teaches the concept of compensating for the heat generated by a chip on one side of a substrate by choosing higher coefficient of thermal expansion insulating layers on the chip side. This concept applies to a bridge chip just as equally to an external chip.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the different coefficient of thermal expansions of Ishida in the invention of Pietambaran because Ishida teaches it prevents short circuiting (column 4, lines 34-40), prevents peeling (column 5, lines 3-7), controls warping (column 5, lines 18-37), and prevents connection failure (column 6, lines 3-16).
With respect to claim 14, though Pietambaran fails to teach the bridge pad (at 123) is on an upper surface of the first core laminated structure 112-1, it would have been obvious to one of ordinary skill in the art at the time of the invention for the first chip mounting space (at 104) is on an upper surface of the first core laminated structure in the invention of Pietambaran because it is a conventionally known equivalent first chip mounting space location. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
As to claim 15, Pietambaran (figure 1) teaches the bridge substrate 104 includes silicon (paragraph 0020 teaches 140 is a through-silicon via therefore 104 is made of silicon), the bridge chip 104 has a third coefficient of thermal expansion (silicon has a third coefficient of thermal expansion), and though Pietambaran fails to teach the third coefficient of thermal expansion is less than the first coefficient of thermal expansion, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative coefficient of thermal expansion through routine experimentation (MPEP 2144.05).
In re claim 16, Pietambaran (figure 1) teaches the bridge chip 104 further includes, a bridge lower pad (at 122) on a lower surface of the bridge substrate 104, a bridge lower connection member 122 electrically connected to the bridge lower pad (at 122) and the first core wiring layers 116, and a bridge through-via 140 passing through the bridge substrate 104 and electrically connecting the bridge lower pad (at 122) to the bridge pad (at 123).
Concerning claim 19, Pietambaran (figure 1) teaches a semiconductor package comprising:
a package substrate 110; and
a first semiconductor chip 102 and a second semiconductor chip 102 mounted on the package substrate 110,
wherein the package substrate 110 includes,
a core substrate 114 including a first surface and a second surface opposite to the first surface,
a first core laminated structure 112-1 on the first surface of the core substrate 114, including a plurality of first core insulating layers 108 and a plurality of first core wirings 116 on the plurality of first core insulating layers 108, and including a first chip mounting space (at 104) defined by the plurality of first core insulating layers 108,
a bridge chip 104 within the first chip mounting space (at 104) and including a bridge substrate 104 and a bridge pad (at 123), and
a second core laminated structure 112-2 on the second surface of the core substrate 114, and including a plurality of second core insulating layers 108 and a plurality of second core wiring layers 116 on the plurality of second core insulating layers 108, and
the first semiconductor chip 102 and the second semiconductor chip 102 are electrically connected to each other through the bridge chip 104.
Pietambaran fails to teach the first core insulating layers have a first coefficient of thermal expansion, and the second core insulating layers have a second coefficient of thermal expansion less than the first coefficient of thermal expansion.
Ishida (abstract) teaches the plurality of first core insulating layers 50A have a first coefficient of thermal expansion, and the plurality of second core insulating layers 50B have a second coefficient of thermal expansion less than the first coefficient of thermal expansion 50A. Though Ishiba fails to each a bridge, Ishaba teaches the concept of compensating for the heat generated by a chip on one side of a substrate by choosing higher coefficient of thermal expansion insulating layers on the chip side. This concept applies to a bridge chip just as equally to an external chip.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the different coefficient of thermal expansions of Ishida in the invention of Pietambaran because Ishida teaches it prevents short circuiting (column 4, lines 34-40), prevents peeling (column 5, lines 3-7), controls warping (column 5, lines 18-37), and prevents connection failure (column 6, lines 3-16).
Pertaining to claim 209, Pietambaran (figure 1) teaches a first portion of the bridge chip 104 vertically overlaps the first semiconductor chip 102, and a second portion of the bridge chip 104 vertically overlaps the second semiconductor chip 102.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/ Primary Examiner, Art Unit 2891 6/25/26
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