Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Specie 2, claims 1-3, 6-14 in the reply filed on 9/4/26 is acknowledged. Claims 4-5 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Oath/Declaration
Oath/Declaration filed on 3/19/24 has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al. (U.S. Patent Publication No. 2015/0333241) in view of HAYAKAWA et al. (U.S. Patent Publication No. 2015/0099317).
Referring to figure 6F, CHEN et al. teaches a semiconductor structure, comprising:
a substrate (30);
a light-emitting structure on the substrate, wherein the light-emitting structure comprises a first type semiconductor layer (321), an active layer (322) and a second type semiconductor layer (323) which are sequentially stacked on the substrate, and the first type semiconductor layer (321) comprises a first portion not covered by the active layer (322).
However, the reference does not clearly teach a first heat-dissipation module at the first portion.
HAYAKAWA et al. a first heat-dissipation module (130) at the first portion (see figure 1), a surface of the first heat-dissipation module away from the substrate is higher than a surface of the active layer away from the substrate (see figure 1, meeting claim 12).
Therefore, it would have been obvious to a person ordinary skill in the requisite art at the time of the invention was filed would form a first heat-dissipation module at the first portion in CHEN et al. as taught by HAYAKAWA et al. because it is known in the art to improve heat extraction from the LED while retaining the exposed semiconductor region in thermal integration.
Claim(s) 2-3, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al. (U.S. Patent Publication No. 2015/0333241) in view of HAYAKAWA et al. (U.S. Patent Publication No. 2015/0099317) as applied to claims 1, 12 and further in view of YU (U.S. Patent Publication No. 2012/0119246).
Referring to figure 6F, CHEN et al. teaches a semiconductor structure, comprising:
a substrate (30);
a light-emitting structure on the substrate, wherein the light-emitting structure comprises a first type semiconductor layer (321), an active layer (322) and a second type semiconductor layer (323) which are sequentially stacked on the substrate, and the first type semiconductor layer (321) comprises a first portion not covered by the active layer (322).
However, the reference does not clearly teach the first conductive structures are at a side of the first heat-dissipation sub-modules and the second heat-dissipation sub-modules facing the substrate, and the second conductive structures are at a side of the first heat-dissipation sub-modules and the second heat-dissipation sub-modules away from the substrate; wherein the first heat-dissipation modules are formed by groups which are connected in series, and each of the groups comprises one of the first heat-dissipation sub- modules, one of the first conductive structures, one of the second heat-dissipation sub- modules and one of the second conductive structures which are connected in series (in claims 2-3); pluralities of heat dissipation sub-modules (in claims 13-14).
Yu et al. teaches a thermoelectric device wherein in a direction parallel to the substrate and along a sidewall of the active layer, the first heat-dissipation module comprises first heat-dissipation sub-modules (58) and second heat-dissipation sub-modules (60) which are arranged alternately (see figures 1M-1N), and a conductive layer that connects the first heat- dissipation sub-modules and the second heat-dissipation sub-modules in series (56, see figure 1G), wherein the first heat-dissipation sub-modules are made of P-type semiconductor thermoelectric materials (58), and the second heat-dissipation sub-modules are made of N-type semiconductor thermoelectric materials (60, see figure 1G-1N, meeting claim 2), the conductive layer (107/56) comprises: first conductive structures (107) disposed apart and second conductive structures (56) disposed apart, wherein the first conductive structures are at a side of the first heat-dissipation sub-modules and the second heat-dissipation sub-modules(58/60) facing the substrate, and the second conductive structures are at a side of the first heat-dissipation sub-modules and the second heat-dissipation sub-modules away from the substrate (see figures 1M-1N); wherein the first heat-dissipation modules are formed by groups which are connected in series, and each of the groups comprises one of the first heat-dissipation sub- modules, one of the first conductive structures, one of the second heat-dissipation sub- modules and one of the second conductive structures which are connected in series (see figures 1G-1N, meeting claim 3); the semiconductor structure further comprises: a second heat-dissipation module on a surface of the light-emitting structure away from the substrate (see figures 1N, 2, meeting claim 13); wherein in a direction parallel to the substrate, the second heat-dissipation module comprises: third heat-dissipation sub-modules and fourth heat-dissipation sub-modules which are alternately arranged, the third heat-dissipation sub-modules are made of P-type semiconductor thermoelectric materials, the fourth heat-dissipation sub-modules are made of N-type semiconductor thermoelectric materials; and fifth conductive structures disposed apart and sixth conductive structures disposed apart, wherein the fifth conductive structures are at a side of the third heat-dissipation sub- modules and the fourth heat-dissipation sub-modules facing the substrate, and the sixth conductive structures are at a side of the third heat-dissipation sub-modules and the fourth heat-dissipation sub-modules away from the substrate; wherein the second heat-dissipation modules are formed by groups which are connected in series, and each of the groups comprises one of the third heat-dissipation sub- modules, one of the fifth conductive structures, one of the fourth heat-dissipation sub- modules and one of the sixth conductive structures which are connected in series (TSVs, 56, 80, 58, 60, see claims 16-17, figures 1G-1N, 2, meeting claim 14).
Therefore, it would have been obvious to a person ordinary skill in the requisite art at the time of the invention was filed would form the first heat-dissipation modules are formed by groups which are connected in series, and each of the groups comprises one of the first heat-dissipation sub- modules, one of the first conductive structures, one of the second heat-dissipation sub- modules and one of the second conductive structures which are connected in series in CHEN et al. as taught by Yu et al. because it is known in the art to improve heat extraction from the LED while retaining the exposed semiconductor region in thermal integration.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN et al. (U.S. Patent Publication No. 2015/0333241) in view of HAYAKAWA et al. (U.S. Patent Publication No. 2015/0099317) as applied to claims 1, 12 and further in view of Lee et al. (U.S. Patent No. 9,941,455).
Referring to figure 6F, CHEN et al. teaches a semiconductor structure, comprising:
a substrate (30);
a light-emitting structure on the substrate, wherein the light-emitting structure comprises a first type semiconductor layer (321), an active layer (322) and a second type semiconductor layer (323) which are sequentially stacked on the substrate, and the first type semiconductor layer (321) comprises a first portion not covered by the active layer (322).
However, the reference does not clearly teach a dielectric layer between the light-emitting structure and the first heat-dissipation module, so that the first heat-dissipation module is electrically isolated from the light- emitting structure (in claim 6); the dielectric layer further covers a sidewall of the light-emitting structure and a surface of the light- emitting structure away from the substrate; and the semiconductor structure further comprises:a first electrode electrically connected to the first type semiconductor layer through a first through-hole which is in the dielectric layer on the first portion; and a second electrode electrically connected to the second type semiconductor layer through a second through-hole which is in the dielectric layer on the second type semiconductor layer (in claim 7).
Lee et al. teaches the semiconductor structure further comprises: a dielectric layer (153) between the light-emitting structure and the first heat-dissipation module (170), so that the first heat-dissipation module is electrically isolated from the light- emitting structure (see figures 44-47, meeting claim 6); the dielectric layer (151/153) further covers a sidewall of the light-emitting structure and a surface of the light- emitting structure away from the substrate; and the semiconductor structure further comprises: a first electrode (140) electrically connected to the first type semiconductor layer through a first through-hole (151a) which is in the dielectric layer on the first portion; and a second electrode (130) electrically connected to the second type semiconductor layer through a second through-hole (151b) which is in the dielectric layer on the second type semiconductor layer (see figures 44-47, meeting claim 7), a material of the dielectric layer is an insulation material, and the dielectric layer comprises a DBR structure (151/153, meeting claim 11).
Therefore, it would have been obvious to a person ordinary skill in the requisite art at the time of the invention was filed would form the dielectric layer further covers a sidewall of the light-emitting structure and a surface of the light- emitting structure away from the substrate in CHEN et al. as taught by Lee et al. because it is known in the art to provide isolation between the structures.
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
