DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I in the reply filed on 07/06/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-10 are rejected under 35 U.S.C. 35 U.S.C. 102(a)(1) as being anticipated by Proschwitz et al. (US PGpub: 2023/0317544 A1), hereinafter Proschwitz.
Regarding claim 1, Proschwitz teaches a package comprising:
a first substrate (133);
a first integrated device (114-1) coupled to the first substrate;
a second substrate (102);
a second integrated device (114-4) coupled to the second substrate; and
a heat sink (156-5) coupled to the second substrate, wherein the heat sink vertically overlaps with at least part of the first integrated device (114-1), and
wherein the heat sink is located laterally to the second integrated device.
Regarding claim 3, Proschwitz teaches the package of claim 1, wherein the first integrated device is coupled to the second substrate through a thermal interface material (TIM) (154, FIG. 1, A TIM 154 may be disposed in the cavity 106 between the substrate 102 and the cooling apparatus 152 and/or on the top surface 172-2 of the circuit board 133 between the circuit board 133 and the cooling apparatus 152. The TIM 154 may help with transferring heat from the die 114 and hastening cooling. The TIM 154 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM 154 may be a thermal interface material paste, a thermal gel, a thermal gad pad, a thermally conductive adhesive, or a thermally conductive epoxy (which may be a fluid when applied and may harden upon curing, as known in the art). The TIM 154 may provide a path for heat generated by the die 114 to readily flow to the cooling apparatus 152, where it may be spread and/or dissipated.).
Regarding claim 4, Proschwitz teaches the package of claim 1, wherein the first integrated device is coupled to the second substrate through solder (154 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM 154 may be a thermal interface material paste, a thermal gel, a thermal gad pad, a thermally conductive adhesive, or a thermally conductive epoxy, FIG. 1B. Paragraph [0030]).
Regarding claim 5, Proschwitz teaches the package of claim 1, wherein the heat sink is coupled to the second substrate through a thermal interface material (154) or solder (Paragraphs [0040]-[0042], FIG. 2).
Regarding claim 6, Proschwitz teaches the package of claim 1, wherein the first integrated device comprises at least one pad interconnect (120) coupled to a back side of the first integrated device (FIG. 1A, Paragraph [0028]).
Regarding claim 7, Proschwitz teaches the package of The package of wherein the second substrate comprises a cavity (106-4 in Proschwitz), the heat sink being coupled to the second substrate through a thermal interface material, the heat sink being coupled to the first integrated device through the thermal interface material, and the heat sink being located at least partially in the cavity of the second substrate (see FIG. 2, Paragraphs [0040]-[0042]).
Regarding claim 8, Proschwitz teaches the package of claim 1, further comprising another integrated device (114-5, FIG. 1B) coupled to the first integrated device,wherein the another integrated device and the first integrated device (114-3) are part of a stack of integrated devices, andwherein the stack of integrated devices is located between the first substrate and the second substrate (stack is located between two substrates).
Regarding claim 9, Proschwitz teaches the package of claim 1, further comprising a third integrated device (114-7) coupled to the second substrate,wherein the heat sink is located laterally between the second integrated device and the third integrated device (156-5 is located between 114-1 and 114-7), and wherein the second integrated device and the third integrated device vertically overlap with at least part the first integrated device (114-3 and 11414-4 overlaps partially).
Regarding claim 10, Proschwitz teaches the package of The package of wherein the second integrated device (114-4) is part of an integrated device package coupled to the second substrate (102), and wherein the integrated device package is coupled to the second substrate through a plurality of solder interconnects (102 is connected to 114-4 via interconnect 120. Paragraph [0028], one or more of the interconnects disclosed herein (e.g., interconnects 120, 130, and 121, as described below with reference to FIG. 2) may include solder bumps or balls (as illustrated in FIG. 1A); in other embodiments, the one or more interconnects 120, 130, 121 may include copper pillars, wirebonds, metal-to-metal interconnects, or any other suitable interconnects. In some embodiments, the one or more interconnects 120, 130, 121 may be surrounded by an underfill material 160. The underfill material 160 may be any suitable material. The underfill material 160 may be an insulating material, such as an appropriate epoxy material. In some embodiments, the underfill material 160 may include a capillary underfill, non-conductive film (NCF), or molded underfill. The underfill material 160 may be selected to have a CTE that may mitigate or minimize the stress between the die 114 and the substrate 102. In some embodiments, the underfill material 160 may include an epoxy flux that assists with soldering the die 114 to the substrate 102 and the substrate 102 to the circuit board 133 when forming the interconnects 120, 130, 121 respectively, and then polymerizes and encapsulates the interconnects 120, 130, 121. In some embodiments, the CTE of the underfill material 160 may have a value that is intermediate to the CTE of the substrate 102 (e.g., the CTE of the dielectric material of the substrate 102) and a CTE of the die 114 and/or the CTE of the circuit board 133. In some embodiments, the one or more interconnects 120, 130, 121 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 35 U.S.C. 103 as being unpatentable over KANG et al. (US PGpub: 2018/0350630 A1), hereinafter KANG, in view of KANG.
Regarding claim 2, Proschwitz does not explicitly teach the package of claim 1, wherein the second substrate includes a plurality of through substrate vias that vertically overlap with at least part of the heat sink and the first integrated device.
However it can be interpreted in Proschwitz that a plurality of through substrate vias that vertically overlap with at least part of the heat sink and the first integrated device. If IC 114-2 position can be replaced with 114-5, then 114-2 which has TSV 115 would partially vertically overlap with the heat sink (The die 114 may be thermally coupled to the cooling apparatus 152 by the TIM 154 and by through-substrate vias (TSVs) 115 in the substrate 102. The TSVs 115 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, other metals or alloys, or combinations of materials, for example, and may be formed using any suitable technique, including through silicon via (TSV) formation techniques. FIG. 1B)
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Proschwitz’s package with other teaching from Proschwitz so that TSVs may serve as electrical connections and/or as thermal vias to dissipate heat from the die..
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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