Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-8, 10-13, and 15-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-11, 13-15, and 17-19 of U.S. Patent No. 12,731985. Although the claims at issue are not identical, they are not patentably distinct from each other. The patented claims disclose all limitations of the claims of the current application.
Current application 18/607,098
US Patent: 12,731,985
A power clamp circuit comprising:
an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage;
a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor;
a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor; and
a third triggering circuit configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs.
A power clamp circuit comprising:
an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage;
a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor;
a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor; and
a third triggering circuit including a third resistor and a third capacitor, and configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs.
2. The power clamp circuit of claim 1, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively, wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein a gate of the second NMOS transistor is coupled to a second gate line, and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor, and wherein a gate of the third NMOS transistor is coupled to a third gate line, and a source of the third NMOS transistor is coupled to the second power rail.
2. The power clamp circuit of claim 1, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively, wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein a gate of the second NMOS transistor is coupled to a second gate line, and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor, and wherein a gate of the third NMOS transistor is coupled to a third gate line, and a source of the third NMOS transistor is coupled to the second power rail.
3.The power clamp circuit of claim 2, wherein the first triggering circuit is configured to:
provide a branch voltage generated by branching the supply voltage to the first gate line, and provide an ESD voltage to the first gate line when the ESD event occurs.
a voltage branch circuit configured to provide a first branch voltage and a second branch voltage,
3. The power clamp circuit of claim 2, wherein the first triggering circuit is configured to provide an ESD voltage to the first gate line when the ESD event occurs, and wherein the second triggering circuit is configured to: provide an ESD voltage to the second gate line when the ESD event occurs.
4. The power clamp circuit of claim 2, wherein the first resistor is disposed between the first power rail and a first node, the first capacitor is disposed between the first node and the second power rail, and the fourth MOS transistor is a first P-channel type (PMOS) transistor, and wherein a gate of the first PMOS transistor is coupled to the first node, a source of the first PMOS transistor is coupled to the first power rail, and a drain of the first PMOS transistor is coupled to the first gate line.
5. The power clamp circuit of claim 3, wherein the first resistor is disposed between the first power rail and a first node, the first capacitor is disposed between the first node and the second power rail, and the fourth MOS transistor is a first P-channel type (PMOS) transistor, and wherein a gate of the first PMOS transistor is coupled to the first node, a source of the first PMOS transistor is coupled to the first power rail, and a drain of the first PMOS transistor is coupled to the first gate line.
5. The power clamp circuit of claim 4, wherein the first triggering circuit further includes a sixth MOS transistor and a seventh MOS transistor that are disposed between the first power rail and the first gate line, and the sixth MOS transistor and the seventh MOS transistor are a fourth NMOS transistor and a fifth NMOS transistor, respectively, wherein a gate of the fourth NMOS transistor is coupled to a branch voltage generated by branching the supply voltage, a drain of the fourth NMOS transistor is coupled to the first power rail, and a source of the fourth NMOS transistor is coupled to a gate of the fifth NMOS transistor, and wherein a drain of the fifth NMOS transistor is coupled to the branch voltage, and a source of the fifth NMOS transistor is coupled to the first gate line.
6. The power clamp circuit of claim 3, wherein the first triggering circuit further includes a sixth MOS transistor and a seventh MOS transistor that are disposed between the first power rail and the first gate line, and the sixth MOS transistor and the seventh MOS transistor are a fourth NMOS transistor and a fifth NMOS transistor, respectively, wherein a gate of the fourth NMOS transistor is coupled to the first branch voltage, a drain of the fourth NMOS transistor is coupled to the first power rail, and a source of the fourth NMOS transistor is coupled to a gate of the fifth NMOS transistor, and wherein a drain of the fifth NMOS transistor is coupled to the first branch voltage, and a source of the fifth NMOS transistor is coupled to the first gate line.
6. The power clamp circuit of claim 5, further comprising a voltage branch circuit configured to provide the branch voltage, wherein the voltage branch circuit includes a plurality of diode-connected MOS transistors coupled in series between the first power rail and the second power rail.
4. The power clamp circuit of claim 3 wherein the voltage branch circuit includes a plurality of diode-connected MOS transistors coupled in series between the first power rail and the second power rail.
7. The power clamp circuit of claim 6, wherein the voltage branch circuit is configured to provide a branch voltage of at least 60% of a voltage applied to the first power rail.
1. wherein the voltage branch circuit is configured to provide the first branch voltage of at least 60% of a voltage applied to the first power rail
8. The power clamp circuit of claim 4, wherein the first triggering circuit further includes an eighth MOS transistor and a ninth MOS transistor that are disposed between the first node and the first capacitor, and the eighth MOS transistor and the ninth MOS transistor are a sixth NMOS transistor and a seventh NMOS transistor, respectively, wherein a gate of the sixth NMOS transistor is coupled to the first gate line, a drain of the sixth NMOS transistor is coupled to the first node, and a source of the sixth NMOS transistor is coupled to a drain of the seventh NMOS transistor, and wherein a gate of the seventh NMOS transistor is coupled to the second gate line, and a source of the seventh NMOS transistor is coupled to the first capacitor.
7. The power clamp circuit of claim 3, wherein the first triggering circuit further includes an eighth MOS transistor and a ninth MOS transistor that are disposed between a first node and the first capacitor, and the eighth MOS transistor and the ninth MOS transistor are a sixth NMOS transistor and a seventh NMOS transistor, respectively, wherein a gate of the sixth NMOS transistor is coupled to the first gate line, a drain of the sixth NMOS transistor is coupled to the first node, and a source of the sixth NMOS transistor is coupled to a drain of the seventh NMOS transistor, and wherein a gate of the seventh NMOS transistor is coupled to the second gate line, and a source of the seventh NMOS transistor is coupled to the first capacitor.
10. The power clamp circuit of claim 2, wherein the second resistor is disposed between the first gate line and a second node, the second capacitor is disposed between the second node and the second power rail, and the fifth MOS transistor is a second PMOS transistor, and wherein a gate of the second PMOS transistor is coupled to the second node, a source of the second PMOS transistor is coupled to the first gate line, and a drain of the second PMOS transistor is coupled to the second gate line.
8. The power clamp circuit of claim 3, wherein the second resistor is disposed between the first gate line and a second node, the second capacitor is disposed between the second node and the second power rail, and the fifth MOS transistor is a second PMOS transistor, and wherein a gate of the second PMOS transistor is coupled to the second node, a source of the second PMOS transistor is coupled to the first gate line, and a drain of the second PMOS transistor is coupled to the second gate line.
11. The power clamp circuit of claim 10, wherein the second triggering circuit further includes a tenth MOS transistor and an eleventh MOS transistor that are disposed between the first gate line and the second gate line, and the tenth MOS transistor and the eleventh MOS transistor are an eighth NMOS transistor and a ninth NMOS transistor, respectively, wherein a gate of the eighth NMOS transistor is coupled to a third node voltage, a drain of the eighth NMOS transistor is coupled to the first gate line, and a source of the eighth NMOS transistor is coupled to a gate of the ninth NMOS transistor, and wherein a drain of the ninth NMOS transistor is coupled to an external power supply voltage that is less than the supply voltage, and a source of the ninth NMOS transistor is coupled to the second gate line.
9. The power clamp circuit of claim 8, wherein the second triggering circuit further includes a tenth MOS transistor and an eleventh MOS transistor that are disposed between the first gate line and the second gate line, and the tenth MOS transistor and the eleventh MOS transistor are an eighth NMOS transistor and a ninth NMOS transistor, respectively, wherein a gate of the eighth NMOS transistor is coupled to the second branch voltage, a drain of the eighth NMOS transistor is coupled to the first gate line, and a source of the eighth NMOS transistor is coupled to a gate of the ninth NMOS transistor, and wherein a drain of the ninth NMOS transistor is coupled to the second branch voltage, and a source of the ninth NMOS transistor is coupled to the second gate line.
12. The power clamp circuit of claim 11, wherein the second triggering circuit further includes a twelfth MOS transistor disposed between the second node and the second capacitor, and the twelfth MOS transistor is a tenth NMOS transistor, and wherein a gate of the tenth NMOS transistor is coupled to the second gate line, a drain of the tenth NMOS transistor is coupled to the second node, and a source of the tenth NMOS transistor is coupled to the second capacitor.
10. The power clamp circuit of claim 9, wherein the second triggering circuit further includes a twelfth MOS transistor disposed between the second node and the second capacitor, and the twelfth MOS transistor is a tenth NMOS transistor, and wherein a gate of the tenth NMOS transistor is coupled to the second gate line, a drain of the tenth NMOS transistor is coupled to the second node, and a source of the tenth NMOS transistor is coupled to the second capacitor.
13. The power clamp circuit of claim 2, wherein the third triggering circuit is configured to: provide the ground voltage to the third gate line, and provide the ESD voltage to the third gate line when the ESD event occurs.
11. The power clamp circuit of claim 3, wherein the third triggering circuit is configured to: provide the ground voltage to the third gate line, and provide an ESD voltage to the third gate line when the ESD event occurs.
15. The power clamp circuit of claim 1, wherein a product of a resistance of the first resistor and a capacitance of the first capacitor is equal to a product of a resistance of the second resistor and a capacitance of the second capacitor.
13. The power clamp circuit of claim 1, wherein a product of a resistance of the first resistor and a capacitance of the first capacitor is equal to a product of a resistance of the second resistor and a capacitance of the second capacitor and a product of a resistance of the third resistor and a capacitance of the third capacitor.
16. An electronic device comprising: a pad; an internal circuit coupled to the pad, a first power rail through which a supply voltage is provided, and a second power rail through which a ground voltage is provided; and a power clamp circuit configured to protect the internal circuit when an electro-static discharge (ESD) event occurs, wherein the power clamp circuit includes: an ESD current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between the first power rail and the second power rail; a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor; a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor; and a third triggering circuit configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when the ESD event occurs.
14. An electronic device comprising: a pad; an internal circuit coupled to the pad, a first power rail through which a supply voltage is provided, and a second power rail through which a ground voltage is provided; and a power clamp circuit configured to protect the internal circuit when an electro-static discharge (ESD) event occurs, wherein the power clamp circuit includes: an ESD current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between the first power rail and the second power rail; a voltage branch circuit configured to provide a first branch voltage and a second branch voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor; a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor; and a third triggering circuit including a third resistor and a third capacitor, and configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when the ESD event occurs, wherein the first triggering circuit is configured to provide the first branch voltage generated by the voltage branch circuit to a gate of the first MOS transistor, wherein the second triggering circuit is configured to provide the second branch voltage generated by the voltage branch circuit to a gate of the second MOS transistor, and wherein the voltage branch circuit is configured to provide the first branch voltage of at least 60% of a voltage applied to the first power rail, and to provide the second branch voltage of at least 30% of a voltage applied to the first power rail.
17. The electronic device of claim 16, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively, wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein a gate of the second NMOS transistor is coupled to a second gate line, and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor, and wherein a gate of the third NMOS transistor is coupled to a third gate line, and a source of the third NMOS transistor is coupled to the second power rail.
15. The electronic device of claim 14, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively, wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein a gate of the second NMOS transistor is coupled to a second gate line, and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor, and wherein a gate of the third NMOS transistor is coupled to a third gate line, and a source of the third NMOS transistor is coupled to the second power rail.
18. The electronic device of claim 17, wherein the first triggering circuit further includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, wherein the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are a first P-channel type MOS (PMOS) transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, respectively, wherein the first resistor is coupled to the first power rail and a first node, wherein gate, source, and drain of the first PMOS transistor are coupled to the first node, the first power rail, and the first gate line, respectively, wherein gate, drain, and source of the fourth NMOS transistor are coupled to a branch voltage generated by branching the supply voltage, the first power rail, and a gate of the fifth NMOS transistor, respectively, wherein drain and source of the fifth NMOS transistor are coupled to the branch voltage and the first gate line, respectively, wherein gate, drain, and source of the sixth NMOS transistor are coupled to the first gate line, the first node, and a drain of the seventh NMOS transistor, respectively, and wherein gate and source of the seventh NMOS transistor are coupled to a second node voltage at the second node and the first capacitor, respectively.
17. The electronic device of claim 16, wherein the first triggering circuit further includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, wherein the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are a first P-channel type MOS (PMOS) transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, respectively, wherein the first resistor is coupled to the first power rail and a first node, wherein gate, source, and drain of the first PMOS transistor are coupled to the first node, the first power rail, and the first gate line, respectively, wherein gate, drain, and source of the fourth NMOS transistor are coupled to the first branch voltage generated by branching the supply voltage, the first power rail, and a gate of the fifth NMOS transistor, respectively, wherein drain and source of the fifth NMOS transistor are coupled to the first branch voltage and the first gate line, respectively, wherein gate, drain, and source of the sixth NMOS transistor are coupled to the first gate line, the first node, and a drain of the seventh NMOS transistor, respectively, and wherein gate and source of the seventh NMOS transistor are coupled to the second gate line and the first capacitor, respectively.
19. The electronic device of claim 18, wherein the second triggering circuit further includes a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor, wherein the fifth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor are a second PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, respectively, wherein the second resistor is coupled to the first gate line and a second node, wherein gate, source, and drain of the second PMOS transistor are coupled to the second node, the first gate line, and the second gate line, respectively, wherein gate, drain, and source of the eighth NMOS transistor are coupled to a third node voltage at the third node, the first gate line, and a gate of the ninth NMOS transistor, respectively, wherein drain and source of the ninth NMOS transistor are coupled to an external power supply voltage that is less than the supply voltage and the second gate line, respectively, and wherein gate, drain, and source of the tenth NMOS transistor are coupled to the second gate line, the second node, and the second capacitor, respectively.
18. The electronic device of claim 17, wherein the second triggering circuit further includes a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor, wherein the fifth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor are a second PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, respectively, wherein the second resistor is coupled to the first gate line and a second node, wherein gate, source, and drain of the second PMOS transistor are coupled to the second node, the first gate line, and the second gate line, respectively, wherein gate, drain, and source of the eighth NMOS transistor are coupled to the second branch voltage, the first gate line, and a gate of the ninth NMOS transistor, respectively, wherein drain and source of the ninth NMOS transistor are coupled to the second branch voltage and the second gate line, respectively, and wherein gate, drain, and source of the tenth NMOS transistor are coupled to the second gate line, the second node, and the second capacitor, respectively.
20. The electronic device of claim 19, wherein the third triggering circuit includes a third resistor, a thirteenth MOS transistor, a fourteenth MOS transistor, and a fifteenth MOS transistor, wherein the thirteenth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor are a third PMOS transistor, a fourth PMOS transistor, and an eleventh NMOS transistor, respectively, wherein the third resistor is coupled to the second power rail and a gate of the third PMOS transistor, wherein a drain of the third PMOS transistor is coupled to the external power supply voltage that is less than the supply voltage, and a source of the third PMOS transistor is coupled to the third node, wherein a gate of the fourth PMOS transistor and a gate of the eleventh NMOS transistor are commonly coupled to the third node, a source of the fourth PMOS transistor is coupled to the second gate line, and a drain of the fourth PMOS transistor and a drain of the eleventh NMOS transistor are commonly coupled to the third gate line, and wherein a source of the eleventh NMOS transistor is coupled to the second power rail.
19. The electronic device of claim 18, wherein the third resistor is disposed between the third gate line and a third node, the third capacitor is disposed between the third node and the second power rail, and an inverter circuit includes a third P-channel type (PMOS) transistor and an eleventh NMOS transistor, wherein a gate of the third PMOS transistor and a gate of the eleventh NMOS transistor are commonly coupled to the third node, a source of the third PMOS transistor is coupled to the second gate line, and a drain of the third PMOS transistor and a drain of the eleventh NMOS transistor are commonly coupled to the third gate line, and wherein a source of the eleventh NMOS transistor is coupled to the second power rail.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10, 13, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li, CN 106410773.
Regarding claim 1, Li discloses a power clamp circuit comprising:
an electro-static discharge (ESD) current discharge circuit [Fig. 2, 1] including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage [Fig. 2, three transistors of 14 are connected in series between the voltage rail and VSS];
a first triggering circuit [Fig. 2, first set of RC circuit of 12] including a first resistor [Fig. 2, first R as shown], a first capacitor [Fig. 2, first capacitor as shown], and a fourth MOS transistor [Fig. 2, a transistor of first inverter set of 13] and configured to trigger the first MOS transistor [Fig. 2, triggers the top/first transistor of 14];
a second triggering circuit [Fig. 2, second set of RC circuit of 12] including a second resistor [Fig. 2, second resistor as shown], a second capacitor [Fig. 2 second capacitor as shown], and a fifth MOS transistor [Fig. 2, a transistor of second inverter set of 13] and configured to trigger the second MOS transistor [Fig. 2, triggers the middle/second transistor of 14]; and
a third triggering circuit configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs [the third/bottom transistor is turned off during normal operation, and turned on during an ESD event to discharge the ESD current].
Regarding claim 2, Li discloses that the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively [Fig. 2 and Fig. 3; discharging transistors of 14 are NMOS as shown],
wherein a gate of the first NMOS transistor is coupled to a first gate line [Fig. 2 line connected between the output of the first inverter set and gate of the first discharge transistor], a drain of the first NMOS transistor is coupled to the first power rail [Fig. 2 and Fig. 3, drain of MN7 is coupled to VDD], and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor [Fig. 3, source of MN7 is coupled to the drain of the middle/second discharge transistor],
wherein a gate of the second NMOS transistor is coupled to a second gate line [Fig. 3, line connected between the output of the second inverter set and the gate of second discharge transistor], and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor [Fig. 3, source of second/middle transistor is coupled to the drain of the bottom/third NMOS transistor], and
wherein a gate of the third NMOS transistor is coupled to a third gate line [Fig. 3, line connected between the output of the third inverter set and the gate of the bottom/third transistor], and a source of the third NMOS transistor is coupled to the second power rail [Fig. 3, source of the third transistor is coupled to VSS].
Regarding claim 3, Li discloses that the first triggering circuit is configured to: provide a branch voltage generated by branching the supply voltage to the first gate line, and provide an ESD voltage to the first gate line when the ESD event occurs [Fig. 3, R1C1 provides a first branch voltage at node f by branching the supply voltage 3VDD to the first inverter set and then provide the inverted voltage to the first gate line (gate of the first transistor MN7].
Regarding claim 4, Li discloses that the first resistor is disposed between the first power rail and a first node [Fig. 3, R1 is disposed between VDD and node f], the first capacitor is disposed between the first node and the second power rail [Fig. 3, C1 is disposed between the node f and VSS], and the fourth MOS transistor [Fig. 3, MP1] is a first P-channel type (PMOS) transistor, and wherein a gate of the first PMOS transistor is coupled to the first node [Fig. 3, gate of MP1 is coupled to the node f], a source of the first PMOS transistor is coupled to the first power rail [Fig. 3, source of MP1 is coupled to VDD], and a drain of the first PMOS transistor is coupled to the first gate line [Fig. 3, drain of MP1 is electrically coupled to the first gate line at node A].
Regarding claim 10, Li discloses that the second resistor is disposed between the first gate line and a second node [Fig. 3, R2 is coupled between the node A and node g], the second capacitor is disposed between the second node and the second power rail [Fig. 3, C2 is disposed between the node g and VSS], and the fifth MOS transistor is a second PMOS transistor, [Fig. 3, top PMOS transistor of a second inverter set connected to the output at node g] and wherein a gate of the second PMOS transistor is coupled to the second node, a source of the second PMOS transistor is coupled to the first gate line, and a drain of the second PMOS transistor is coupled to the second gate line [Fig. 3, gate of PMOS transistor is coupled to the node g, the source of the second PMOS transistor is coupled to the first gate line at node A, and drain terminal of the second PMOS transistor is coupled to the second gate line at node B].
Regarding claim 13, Li discloses that the third triggering circuit is configured to: provide the ground voltage to the third gate line, and provide an ESD voltage to the third gate line when the ESD event occurs [Fig. 3, third NMOS discharge transistor is turned off during normal operation and the third set of RC circuit triggers the gate of the third discharge transistor during an ESD condition].
Regarding claim 16, Li discloses an electronic device comprising: a pad [Fig. 3 and Fig. 5, input/output pad of the circuit];
an internal circuit coupled to the pad [IC is inherently coupled to the pad and ESD circuit], a first power rail through which a supply voltage is provided [Fig. 3. VDD], and a second power rail [Fig. 3, VSS] through which a ground voltage is provided; and
a power clamp circuit configured to protect the internal circuit when an electro- static discharge (ESD) event occurs, wherein the power clamp circuit includes:
an electro-static discharge (ESD) current discharge circuit [Fig. 2, 1] including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage [Fig. 2, three transistors of 14 are connected in series between the voltage rail and VSS];
a first triggering circuit [Fig. 2, first set of RC circuit of 12] including a first resistor [Fig. 2, first R as shown], a first capacitor [Fig. 2, first capacitor as shown] and a fourth MOS transistor [Fig. 2, a transistor of first inverter set of 13] and configured to trigger the first MOS transistor [Fig. 2, triggers the top/first transistor of 14];
a second triggering circuit [Fig. 2, second set of RC circuit of 12] including a second resistor [Fig. 2, second resistor as shown], a second capacitor [Fig. 2, second capacitor as shown], and a fifth MOS transistor [Fig. 2, a transistor of second inverter set of 13] and configured to trigger the second MOS transistor [Fig. 2, triggers the middle/second transistor of 14]; and
a third triggering circuit [Fig. 2, third set of RC circuit of 12] including a third resistor and a third capacitor [Fig. 2, third resistor and capacitor as shown], and configured to turn off the third MOS transistor during a normal operation and to turn on the third MOS transistor when an ESD event occurs [the third/bottom transistor is turned off during normal operation, and turned on during an ESD event to discharge the ESD current].
Regarding claim 17, Li discloses that the first MOS transistor, the second MOS transistor, and the third MOS transistor are a first N-channel type MOS (NMOS) transistor, a second NMOS transistor, and a third NMOS transistor, respectively [Fig. 2 and Fig. 3; discharging transistors of 14 are NMOS as shown],
wherein a gate of the first NMOS transistor is coupled to a first gate line [Fig. 2, line connected between the output of the first inverter set and gate of the first discharge transistor], a drain of the first NMOS transistor is coupled to the first power rail [Fig. 2 and Fig. 3, drain of MN7 is coupled to VDD] and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor [Fig. 3, source of MN7 is coupled to the drain of the middle/second discharge transistor];
wherein a gate of the second NMOS transistor is coupled to a second gate line [Fig. 3, line connected between the output of the second inverter set and the gate of second discharge transistor], and a source of the second NMOS transistor is coupled to a drain of the third NMOS transistor [Fig. 3, source of second/middle transistor is coupled to the drain of the bottom/third NMOS transistor], and
wherein a gate of the third NMOS transistor is coupled to a third gate line [Fig. 3, line connected between the output of the third inverter set and the gate of the bottom/third transistor] and a source of the third NMOS transistor is coupled to the second power rail [Fig. 3, source of the third transistor is coupled to VSS].
Allowable Subject Matter
Claims 5-9, 11-12, 14-15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 5: The prior art does not disclose that the first triggering circuit further includes a sixth MOS transistor and a seventh MOS transistor that are disposed between the first power rail and the first gate line, and the sixth MOS transistor and the seventh MOS transistor are a fourth NMOS transistor and a fifth NMOS transistor, respectively, wherein a gate of the fourth NMOS transistor is coupled to a branch voltage generated by branching the supply voltage, a drain of the fourth NMOS transistor is coupled to the first power rail, and a source of the fourth NMOS transistor is coupled to a gate of the fifth NMOS transistor, and wherein a drain of the fifth NMOS transistor is coupled to the branch voltage, and a source of the fifth NMOS transistor is coupled to the first gate line. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 8: The prior art does not disclose that the first triggering circuit further includes an eighth MOS transistor and a ninth MOS transistor that are disposed between the first node and the first capacitor, and the eighth MOS transistor and the ninth MOS transistor are a sixth NMOS transistor and a seventh NMOS transistor, respectively, wherein a gate of the sixth NMOS transistor is coupled to the first gate line, a drain of the sixth NMOS transistor is coupled to the first node, and a source of the sixth NMOS transistor is coupled to a drain of the seventh NMOS transistor, and wherein a gate of the seventh NMOS transistor is coupled to the second gate line, and a source of the seventh NMOS transistor is coupled to the first capacitor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 9: The prior art does not disclose that the second triggering circuit is configured to: provide an external power supply voltage that is less than the supply voltage to the second gate line, and provide the ESD voltage to the second gate line when the ESD event occurs. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 11: The prior art does not disclose that the second triggering circuit further includes a tenth MOS transistor and an eleventh MOS transistor that are disposed between the first gate line and the second gate line, and the tenth MOS transistor and the eleventh MOS transistor are an eighth NMOS transistor and a ninth NMOS transistor, respectively, wherein a gate of the eighth NMOS transistor is coupled to a third node voltage, a drain of the eighth NMOS transistor is coupled to the first gate line, and a source of the eighth NMOS transistor is coupled to a gate of the ninth NMOS transistor, and wherein a drain of the ninth NMOS transistor is coupled to an external power supply voltage that is less than the supply voltage, and a source of the ninth NMOS transistor is coupled to the second gate line. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 14: The prior art does not disclose that the third triggering circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, and a fifteenth MOS transistor, and the thirteenth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor are a third PMOS transistor, a fourth PMOS transistor, and an eleventh NMOS transistor, respectively, wherein the third resistor is coupled to the second power rail and a gate of the third PMOS transistor, a drain of the third PMOS transistor is coupled to an external power supply voltage that is less than the supply voltage, and a source of the third PMOS transistor is coupled to a third node, wherein a gate of the fourth PMOS transistor and a gate of the eleventh NMOS transistor are commonly coupled to the third node, a source of the fourth PMOS transistor is coupled to the second gate line, and a drain of the fourth PMOS transistor and a drain of the eleventh NMOS transistor are commonly coupled to the third gate line, and wherein a source of the eleventh NMOS transistor is coupled to the second power rail. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 15: The prior art does not disclose that a product of a resistance of the first resistor and a capacitance of the first capacitor is equal to a product of a resistance of the second resistor and a capacitance of the second capacitor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 18: The prior art does not disclose that the first triggering circuit further includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, wherein the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are a first P-channel type MOS (PMOS) transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, respectively, wherein the first resistor is coupled to the first power rail and a first node, wherein gate, source, and drain of the first PMOS transistor are coupled to the first node, the first power rail, and the first gate line, respectively, wherein gate, drain, and source of the fourth NMOS transistor are coupled to a branch voltage generated by branching the supply voltage, the first power rail, and a gate of the fifth NMOS transistor, respectively, wherein drain and source of the fifth NMOS transistor are coupled to the branch voltage and the first gate line, respectively, wherein gate, drain, and source of the sixth NMOS transistor are coupled to the first gate line, the first node, and a drain of the seventh NMOS transistor, respectively, and wherein gate and source of the seventh NMOS transistor are coupled to a second node voltage at the second node and the first capacitor, respectively.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838
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