Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments with respect to claims 1-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14, & 20-29 are rejected under 35 U.S.C. 103 as being unpatentable over Blasco et al. PG Pub US 2023/0064603 Al [hereinafter Blasco] in view of Ohtsuki Patent US 5,101,346 [hereinafter Ohtsuki].
Regarding claims 1, 22, & 29, Blasco discloses:
comprising a plurality of processor cores (cores) communicatively coupled to each other (processors 204-1 to 204-N and 206-1 to 206-N), and configured to couple to a memory system (Memory 104), wherein: each core of the plurality of cores comprises a core translation look-aside buffer (TLB) (A TLBI instruction identifies one or more entries of an associated table lookaside buffer (TLB) to be invalidated [0043]) configured to store copies of page table entries of a virtual machine (VM) (a data fetch request retrieves data that includes a virtual address to physical address translation or a virtual address to physical address mapping, which may be, for example, a page entry in a page table [0042]);
each core of the plurality of cores is allocated to one or more of a plurality of sets of cores comprising a first set of cores (this limitation is unclear, for this examination it is interpreted as cores are grouped in “sets” such as in a SOC 102 or cluster 202.); and
a first core of the plurality of cores is configured to: obtain first information that identifies cores in the first set of cores and indicates that at least one core in the first set of cores is assigned to execute instructions of a first VM (each of the filters 232 associated with a respective cluster cache 212 and each of the filters 230 associated with a respective core cache 218 are queried to determine whether the respective cache stores cache entries associated the identifier specified in the TLBI instructions [0043]); and
send a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM in the core TLBs in the first set of cores (with a determination that the respective cache stores one or more cache entries associated with the one or more identifiers specified in the TLBI instruction, the TLBI instruction is executed at the respective cache [0044]).
It is noted that Blasco is broadcasting the invalidation message, however, Ohtsuki discloses sending the invalidation command to only the processors with a correspondence relation to the virtual machine [Col. 4 lines 26-65].
The systems of Blasco and Ohtsuki are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Blasco and Ohtsuki since this would result in the system of Blasco only sending the invalidate command to the processors related to the particular VM. This system would improve system efficiency [Col. 1 Line23 to Col. 2 Line 2].
Regarding claim 2 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein the first information further indicates that instructions of the first VM are only executed in the first set of cores (this is the case where the TLB in cache 220 indicates that the only TLB to be invalidated is located in cluster 1 according to the VMID as seen in Fig. 4A).
Regarding claims 3 & 23 the limitations of these claims have been noted in the rejection of claims 1 & 22. Blasco also discloses:
wherein the first message is directed to only the first set of cores (this is the case where the TLB in cache 220 indicates that the only TLB to be invalidated is located in cluster 1 according to the VMID as seen in Fig. 4A).
Regarding claims 4 & 24 the limitations of these claims have been noted in the rejection of claims 1 & 22. Blasco also discloses:
further comprising a third set of cores (Cluster 202-3), wherein: the first information further indicates that at least one core in the third set of cores is assigned to execute instructions of the first VM; and the first message is also directed to the third set of cores (a first processor (such as processor 204-1, shown in FIG. 2) issues (step 412) a TLBI instruction in response to a user action (step 410), such as a user action to shut down a virtual machine. The TLBI instruction includes instructions to invalidate translation information associated with a first VMID such that when the TLBI instruction is executed at a cache, cache entries in the cache that are associated with the first VMID are invalidated or removed from the cache. In this example, the TLBI instruction does not identify a particular ASID nor a particular VAID by which to invalidate TLB entries [0053]).
Regarding claim 5 the limitations of this claim have been noted in the rejection of claim 4. Blasco also discloses:
wherein: the plurality of sets of cores further comprises a second set of cores (Cluster 202-2); the first information further indicates that no core in the second set of cores is assigned to execute instructions of the first VM; and the first message is not directed to the second set of cores (In accordance with a determination that the respective cache does not store any cache entries associated with an identifier specified in the TLBI instruction, the TLBI instruction is not executed at the respective cache [0044]).
Regarding claims 6 & 26 the limitations of these claims have been noted in the rejection of claims 1 & 22. Blasco also discloses:
the first information further indicating that at least one core in the first set of cores is assigned to execute instructions of a second VM (a first processor (such as processor 204-1, shown in FIG. 2) issues (step 412) a TLBI instruction in response to a user action (step 410), such as a user action to shut down a virtual machine. The TLBI instruction includes instructions to invalidate translation information associated with a first VMID such that when the TLBI instruction is executed at a cache, cache entries in the cache that are associated with the first VMID are invalidated or removed from the cache. In this example, the TLBI instruction does not identify a particular ASID nor a particular VAID by which to invalidate TLB entries [0053]).
Regarding claim 7 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein: the plurality of cores is disposed in clusters; and the first set of cores comprises cores of a first cluster (electronic device 200 having one or more processing clusters 202 (e.g., first processing cluster 202-1, Mth processing cluster 202-M) [0033]).
Regarding claim 8 the limitations of this claim have been noted in the rejection of claim 7. Blasco also discloses:
wherein the first set of cores consists of cores in the first cluster (electronic device 200 having one or more processing clusters 202 (e.g., first processing cluster 202-1, Mth processing cluster 202-M) [0033]).
Regarding claim 9 the limitations of this claim have been noted in the rejection of claim 8. Blasco also discloses:
wherein the first set of cores comprises all the cores in the first cluster (electronic device 200 having one or more processing clusters 202 (e.g., first processing cluster 202-1, Mth processing cluster 202-M) [0033]).
Regarding claim 10 the limitations of this claim have been noted in the rejection of claim 7. Blasco also discloses:
wherein the first set of cores further comprises cores of a second cluster (if a new cache entry that includes a first virtual machine identifier (VMID) is stored at first cluster cache 212-1, the one or more filters 232-1 associated with the first cluster cache 212-1 is updated to store information indicating that the first cluster cache 212-1 stores at least one cache entry with the first VMID [0036]).
Regarding claim 11 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein the first core is further configured to read the first information from a data structure in the memory system (the one or more filter(s) 232-1 associated with the first cluster cache 212 are updated to store information regarding the newly added cache entries [0036] the first information is stored in the filter).
Regarding claim 12 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein the first core is further configured to read the first information from a storage circuit coupled to the plurality of cores (each of the filters 232 associated with a respective cluster cache 212 and each of the filters 230 associated with a respective core cache 218 are queried [0043]).
Regarding claim 14 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein a core of the plurality of cores is configured to update the first information in response to instructions of a hypervisor or a second VM assigned to a core in the first set of cores (The hypervisor 310 hosts one or more virtual machines 320 (e.g., virtual machines 320-1 through 320-m) and each of the virtual machines 320 runs a respective guest operating system (OS) 324 and one or more respective guest applications 322 [0045]).
Regarding claim 20 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
further comprising an input/output (I/O) port communicatively coupled to the plurality of cores (this is the connection between cache 220 and clusters 202 in Fig. 2) and comprising a port TLB configured to store copies of page table entries of a VM (this is the TLB stored in the 220 cache), wherein: the first information indicates that the port TLB stores a copy of at least one page table entry of the first VM (In accordance with a determination that the respective cache stores one or more cache entries associated with the one or more identifiers specified in the TLBI instruction, the TLBI instruction is executed at the respective cache and one or more filters associated with the respective cache [0044]); and the first core is further configured to send the first message to the I/O port to invalidate the copy of the first page table entry in the port TLB (a first processor (such as processor 204-1, shown in FIG. 2) issues (step 412) a TLBI instruction in response to a user action (step 410) [0053]).
Regarding claim 21 the limitations of this claim have been noted in the rejection of claim 20. Blasco also discloses:
wherein: the I/O port is configured to couple to at least one external device comprising a device TLB configured to store copies of page table entries of a VM (it is not clear if the “external device” is the cluster external to cluster 202-1 containing processor 204. If it is than the external device is cluster 202 2-M); the first information indicates that a first external device of the at least one external device is assigned to execute instructions of the first VM; and the first core is further configured to send the first message to the external device (The TLBI instruction includes instructions to invalidate translation information associated with a first VMID such that when the TLBI instruction is executed at a cache, cache entries in the cache that are associated with the first VMID are invalidated or removed from the cache [0053]).
Regarding claim 25 the limitations of this claim have been noted in the rejection of claim 22. Blasco also discloses:
further comprising: assigning only cores in the first set of cores to execute instructions of the first VM; and directing the first message to only the first set of cores (this is the case where the TLB in cache 220 indicates that the only TLB to be invalidated is located in cluster 1 according to the VMID as seen in Fig. 4A).
Claims 13 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Blasco in view of Ohtsuki further in view of Campbell et al. PG Pub US 2022/0035748 A1.
Regarding claim 13, the limitations of this claim have been noted in the rejection of claim 1, it is noted that Blasco failed to explicitly disclose:
wherein the first core is further configured to: receive acknowledgements of the first message from each core in the first set of cores; and in response to receiving the acknowledgements, update the first page table entry in a page table in the memory system.
However, Campbell discloses:
wherein the first core is further configured to: receive acknowledgements of the first message from each core in the first set of cores; and in response to receiving the acknowledgements, update the first page table entry in a page table in the memory system (Marking the load/store operations matching the set/way of the cache entry that is invalidated ensures that all load/store operations to the page being invalidated are finished before acknowledging completion of the TLB invalidate instruction to the originating core [0002]).
The systems of Blasco and Campbell are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Blasco and Campbell since this would enable the system of Blasco to send a single invalidation command from a given cluster to all of the other clusters. This system ensures that the out of order requirement is satisfied [0002].
Regarding claim 15 the limitations of this claim have been noted in the rejection of claim 1. Blasco also discloses:
wherein: the plurality of cores is disposed in one or more clusters of cores (shown in Fig. 2);
each cluster of the one or more clusters of cores comprises a home core configured to execute instructions affecting all cores in the cluster;
the first core is configured to transmit the first message to the home core of each one of the one or more clusters comprising at least one core of the first set of cores (The first processor transmits (step 434) the TLBI instruction to each cache in the system module 100 (e.g., including core caches 218-1, . . . , 218-N, . . . 218-N′, cluster caches 212-1, . . . , 212-M, and cache 220) [0054]); and
the home core of each one of the one or more clusters forwards the first message to the cores in the cluster.
It is noted that Blasco failed to explicitly disclose:
each cluster of the one or more clusters of cores comprises a home core configured to execute instructions affecting all cores in the cluster;
the home core of each one of the one or more clusters forwards the first message to the cores in the cluster.
However, Campbell discloses:
each cluster of the one or more clusters of cores comprises a home core configured to execute instructions affecting all cores in the cluster ([0013]);
the home core of each one of the one or more clusters forwards the first message to the cores in the cluster (The core performing the invalidation of its cached TLB entries (i.e., the originating or home core) broadcasts the TLB invalidation instruction to the remaining cores (i.e., the remote cores) in the system over the interconnect hardware fabric that connects all the cores [0013]).
The systems of Blasco and Campbell are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Blasco and Campbell since this would enable the system of Blasco to send a single invalidation command from a given cluster to all of the other clusters. This system ensures that the out of order requirement is satisfied [0002].
Allowable Subject Matter
Claims 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/SEAN D ROSSITER/ Primary Examiner, Art Unit 2133