Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 24, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Wafer Test System and Test Method.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-9, 11-15, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai et. al. (US Patent 2021/0239736 A1) .
The applied reference has a common applicant and joint inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1 and 11, Tsai et. al. discloses a test system and test method, comprising: an assessment subsystem (Abstract) configured to: receive a test data from a wafer test apparatus, wherein the test data comprises a test image of a wafer; receive an analyzed yield data of the wafer (Figure 5, S510-S530); and receive an identification data based on the test image (Figure 5, S530, image specification from probe apparatus); an optical check subsystem (Figure 5, S540, Probe mark assessment subsystem); and a process control processor configured: in response to the wafer test apparatus to perform a test operation to generate the test data (error-monitoring subsystem 106, processor 600 in Figure 1); in response to the optical check subsystem to identify an image specification of probe marks in the test image and to generate the identification data (Figure 5, S530, automated assessment of a probe mark); and in response to the assessment subsystem to perform an assessment operation to generate an assessment result based on the test data, the analyzed yield data, and the identification data (Figure 5, S540-S550).
Regarding claim 2, Tsai et. al. discloses the test system of claim 1, wherein the process control processor is further configured to transmit the test data, the analyzed yield data, and the identification data to the assessment subsystem in an automation mode (Figure 5, S540, the automated assessment of the probe mark).
Regarding claim 3 and 15, Tsai et. al. discloses the test system of claim 1 and method of claim 11, wherein the process control processor is further configured to perform a verification operation on the wafer to generate the analyzed yield data ([0048]-[0049], determination of threshold value by probe mark inspection).
Regarding claim 4, Tsai et. al. discloses the test system of claim 1, further comprising: a database server connected to the process control processor and configured to save the test data, the analyzed yield data, and the identification data (Figure 1, data server 102).
Regarding claim 5, Tsai et. al. discloses the test system of claim 4, wherein the database server is further connected to the assessment subsystem and configured to save the assessment result (Figure 1, data server 102).
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Regarding claim 8 and 12, Tsai et. al. discloses the test system of claim 1 and the test method of claim 11, wherein the assessment operation comprises determining whether the test data, the analyzed yield data, and the identification data meet a plurality of quality thresholds (Figure 4, [0046]-[0049]).
Regarding claim 9, 13, and 14, Tsai et. al. discloses the test system of claim 8 and the method of claim 12, wherein if the test data, the analyzed yield data, and the identification data meet the quality thresholds, the assessment result indicates a pass result, and wherein if anyone of the test data, the analyzed yield data, and the identification data fails to meet the quality thresholds, the assessment result indicates a failure result (Figure 5, S540-S550).
Regarding claim 20, Tsai et. al. discloses the test method of claim 11, further comprising: transmitting the test data, the analyzed yield data, and the identification data to the assessment subsystem (Figure 5, S540).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6-7, 10, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US Patent 2021/0239736 A1) in view of Tabor (US Patent 2003/0014205 A1).
Regarding claim 6 and 18, Tsai et. al. discloses the test system of claim 1 and test method of claim 11. However, Tsai et. al. fails to disclose further comprising: a recipe server connected to the process control processor and configured to save and obtain recipe data corresponding to the wafer test apparatus.
Tabor teaches a recipe server connected to the process control processor and configured to save a recipe data corresponding to the wafer test apparatus ([0038], criteria is stored in a recipe file for easy access; [0031] which is stored in a remote server 116 at a main production server for a manufacturing facility). It is important to the claimed invention to have a recipe server to allow for easy-to-use interface when handling additional recipes containing wafer criteria for production. Thus, it would have been obvious to one skilled in the art prior to the effective filing date of the claimed invention to have combined the teachings of Tsai et. al. and the teachings of Tabor to have a recipe server that allows for robust data storage.
Regarding claim 7, 10, 16, and 17 Tsai et. al. discloses the test system of claim 1 and test method of claim 11. However, Tsai et. al. fails to disclose wherein the image specification and test data comprises a distribution of probes of a probe card of the wafer test apparatus, a distance between the probes of the probe card and a surface of the wafer, a specification of the probes of the probe card, or a combination thereof.
Tabor specifically teaches wherein the image specification and test data comprises a distribution of probes of a probe card of the wafer test apparatus, a distance between the probes of the probe card and a surface of the wafer, a specification of the probes of the probe card, or a combination thereof ([0030], where the memory 112 stores a component identifier based on the coordinate position on the wafer map for the test wafer). It is critical for the claimed invention to have the precise location and information associated with each wafer component to better identify the desired wafer standard. Thus, it would have been obvious to one skilled in the art prior to the effective filing date of the claimed invention to combine the teachings of Tsai et. al. with the teachings of Tabor to include precise component identifier for each wafer component tested.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. and Tabor as applied to claim 18 above, and further in view of Humphrey et. al. (US Patent 11035898 B1).
Regarding claim 19, Tsai et. al. and Tabor disclose the test method of claim 18. However, Tsai et. al. and Tabor fail to disclose wherein performing the test operation comprises: heating a probe card of the wafer test apparatus based on the recipe data; and performing a clean operation on probes of the probe card based on the recipe data.
Humphrey et. al. teaches wherein performing the test operation comprises: heating a probe card of the wafer test apparatus based on the recipe data; and performing a clean operation on probes of the probe card based on the recipe data (Figure 5, col 3, lines 55-67 method of heating the probe card, and col 9, lines 61-65 through col 10, lines 1-2, cleaning of the probe card.). It is important to create thermal stability for the probe card and also a method for cleaning to avoid contamination of the products for the claimed invention. Wafer testing at low and/or elevated temperatures are essential to facilitate proper test program execution and defect identification. Thus, it would have been obvious for one skilled in the art prior to the effective filing date of the claimed invention to have included the teachings of Humphrey et. al. with the combined teachings of Tsai et. al. and Tabor so that there is a heating element and cleaning operation for the probe card. This would allow for increased accuracy in the wafer testing process to also identify faults within the performance of semiconductor devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSICA YIFANG LIN whose telephone number is (571)272-6435. The examiner can normally be reached M-F 7:00am-6:15pm, with optional day off.
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/JESSICA YIFANG LIN/
Examiner, Art Unit 2668
January 13, 2026
/VU LE/Supervisory Patent Examiner, Art Unit 2668