DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, drawn to claims 1-5 and 14, in the reply filed on 07/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 6-13 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/26/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta et al. (US 20180350921 A1), hereinafter referred to as Dasgupta921, in view of Then et al. (US 20130271208 A1) hereinafter referred to a Then208.
Regarding claim 1: Dasgupta921 teaches a semiconductor power device (“the TMDCOGOS substrate offers the further advantage of monolithically integrating III-N devices suitable for high-voltage and high-frequency applications”, para. [0023]), comprising: a substrate (See Fig. 3A, silicon layer 320), having a circuit region (TMDC device region 307 and silicon device region 308, see Fig. 3A annotated below) and a power device region (III-N device region 306, see Fig. 3A annotated below); a buffer layer, disposed on the substrate (“semiconductor layer 230A includes a buffer layer disposed directly on silicon layer 320”, para. [0043]); a nitride channel layer (Dasgupta921 teaches that the top surface of the III-N layer 230A is GaN, para. [0045], which is listed in the specification of the instant case as a nitride channel layer material, see para. [0048], the examiner also notes that GaN is listed as a buffer layer material in the specification of the instant case, see para. [0048], therefore a monocrystalline structure of GaN could be considered both the buffer layer and the nitride channel layer, see Fig. 3A annotated below) disposed on the buffer layer; a barrier layer disposed on the nitride channel layer (“a polarization layer 236 is disposed directly on a layer of III-N semiconductor layer 230A.”, para. [0045]); drive circuitry disposed on the substrate in the power device region (“Higher-voltage drive circuitry may be further implemented in n-channel III-N (e.g., GaN) devices within region 306., para. [0061]); and a complementary logic circuit, disposed on the substrate in the circuit region and electrically connected to the driving circuitry (The examiner notes that the driving circuitry must necessarily be electrically connected to the other circuits of the device to drive them), and comprising: a P-type transistor, comprising a two-dimensional (2D) material channel layer (“TMDC layer 235 disposed on one or more of the top surface and sidewalls of fins 230C may be functional as a device layer (e.g., suitable as a channel of a FET”, para. [0059]) and an N-type transistor, electrically connected to the P-type transistor (“For example, substrate 303 may be particularly well suited for integration of n-channel Si double-gate and/or tri-gate transistors within region 308 and p-channel TMDC transistors within region 307. The combination of which may implement CMOS logic circuitry.”, para. [0061], the examiner notes that if the p-type and n-type transistors are capable of CMOS logic operations then they are necessarily electrically connected), wherein a two-dimensional electron gas (2DEG) is located in the nitride channel layer and adjacent to an interface between the nitride channel layer and the barrier layer (“polarization layer 236 induces a 2 DEG of high charge density and mobility within III-N semiconductor proximate to the interface of polarization layer 236.”, para. [0046]).
Dasgupta921 does not explicitly teach that the drive circuitry is a power transistor.
Then201 teaches a III-N transistor for integrating high voltage power management with low power CMOS data processing (para. [0018]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to look to the prior art to find examples of high-power driving circuity used in conjunction with low power complementary logic operations, as Dasgupta921 does not explicitly teach the structure of the high-power driving circuitry. The use of a III-N transistor as a component of high voltage driving circuitry, as taught by Then201 is well-known in the art and could be combined with the teachings of Dasgupta921 by known methods to arrive at the claimed invention. A person of ordinary skill in the art would have recognized that such a combination would yield predictable results.
Regarding claim 2: In addition to the reasoning used to reject claim 1, Dasgupta921 teaches that the 2DEG is located only in the power device region (The 2DEG exists at the interface of the polarization layer 326 and III-N layer 230A, which exists only III-N device region 306, see Fig. 3A annotated below).
Regarding claim 3: In addition to the reasoning used to reject claim 2, Then201 teaches (See at least Fig. 1A) the 2DEG (element 111) is located below a gate (element 120), a source (element 135A) and a drain (element 145A) of the power transistor.
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Close up of Fig. 3A from Dasgupta921: A monocrystalline GaN region (230A) could be arbitrarily divided into a top (black dashed box) and bottom portion (red dashed box) to represent the Nitride channel layer and Buffer layer respectively.
Regarding claim 14: In addition to the reasoning used to reject claim 1, Dasgupta921 teaches a material of the 2D material channel layer comprises graphene, silicene, boron nitride nanosheet, transition metal dichalcogenide, phosphorene, metal oxide nanosheet or Group II-VI compound. (“TMDC (transition metal dichalcogenide) layer 235 disposed on one or more of the top surface and sidewalls of fins 230C may be functional as a device layer (e.g., suitable as a channel of a FET”, para. [0059]).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta et al. (US 20180350921 A1), hereinafter referred to as Dasgupta921, in view of Cho (US 20210020765 A1) hereinafter referred to as Cho765 and Then et al. (US 20130271208 A1) hereinafter referred to a Then208.
Regarding claim 4: In addition to the reasoning used to reject claim 3, Dasgupta921 and Then208 teach a front-gated electrode structure. They do not teach the back-gated electrode structure of claim 4.
Cho765 teaches (See Fig. 1) a transistor wherein each of the P- type transistor and the N-type transistor (“a single element can operate in n-type or in p-type according to the sign of the source-drain voltage.”, para. [0022]) comprises a gate (element 20), disposed on the barrier layer (compound semiconductor substrate 10, see para. [0050]); a dielectric layer (“an insulating film such as SiO.sub.2 may be formed thereon as a buffer layer.” Para. [0050]), disposed between the gate and the barrier layer (insulating film (dielectric layer) is the top part of compound semiconductor substrate 10); a channel layer (element 40), disposed on the gate; a gate dielectric layer (element 30), disposed between the gate and the channel layer; and a source (element 91) and a drain (element 93), disposed on the channel layer, wherein the channel layer is the 2D material channel layer (See para. [0052] for description of 2D material), (See also para. [0049] for transistor structure). Cho765 additionally teaches that such transistors are suitable for CMOS logic operations (“Accordingly, a high-performance complementary TFET can be implemented to replace a CMOS transistor, and, ultimately, Moore's law can be extended.”, para. [0022]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to look to the current state of the art to find transistors containing 2D materials as described in Dasgupta921 that would be suitable for complimentary logic operations. The transistor structure taught by Cho765 could be substituted as the TMDC device disclosed in Dasgupta921 to arrive at the claimed invention with a reasonable expectation of success, since the substituted components and their function were well-known in the art.
Regarding claim 5: In addition to the reasoning used to reject claims 3 and 4, Cho765 teaches (See Fig. 1) each of the P- type transistor and the N-type transistor (“a single element can operate in n-type or in p-type according to the sign of the source-drain voltage.”, para. [0022]) comprises: a channel layer (element 40), disposed on the barrier layer (element 10); a dielectric layer (“an insulating film such as SiO.sub.2 may be formed thereon as a buffer layer.” Para. [0050]), disposed between the channel layer and the barrier layer; a gate (element 92) a source (element 91) and a drain (element 93), disposed on the channel layer; and a gate dielectric layer (element 71), disposed between the gate and the channel layer, wherein the channel layer is the 2D material channel layer (2D material layer 40).
The transistor taught by Cho765 has a gate electrode on the top and bottom of the transistor stack and thus reads on both claim 4 and claim 5. Furthermore, the reasoning used to reject claim 4 also applies to claim 5.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Kim et al. (US 20140183453 A1) teaches the 2D transistor structure for the circuit region of the claimed device. Teo et al. (US 20170018638 A1) teaches the power transistor structure of the claimed device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
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