Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This office action is in response to the filing with the office dated 03/17/2024.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 03/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claim 9 is rejected under 35 US.C. 112 as being indefinite for reciting method steps of using the apparatus of claim 1.
Claim 9 recites “A test method for the semiconductor device according to claim 1, the test method comprising:………”.
A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite. Ex parte Lyell, 17 USPQ2d 1548 (Bd. Pat. App. & Inter. 1990). Such a claim is directed to neither a “process” nor a “machine,” but rather embraces or overlaps two different statutory classes of invention. MPEP § 2173.05(p).
Allowable subject matter
5. Claim 1 is allowed.
6. Claims 2-8 are allowed due to their dependency on claim 1.
In related Art, Kitagawa (US 2017/006017 A1) teaches, a semiconductor device includes: a clock generation circuit configured to receive a first clock signal and to generate a second clock signal from the first clock signal; a first phase adjustment circuit configured to generate a first control signal using the first clock signal and the second clock signal; and a second phase adjustment circuit configured to receive data and to add a first delay value based on the first control signal to the data.
Baba et al (US 2004/0109476 A1) teaches, A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.
Tokunaga (US 8055964 B2) teaches, A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits, a clock oscillator which generates a plurality of clock signals corresponding to respective operating frequencies that are used to test the plurality of clock domains, a scan clock signal input circuit which receives, from an outside, and a scan clock signal that is supplied to the plurality of scan chains. The semiconductor device further includes a pulse generation circuit unit which generates a clock pulse signal used for the testing based on the clock signal and the scan clock signal, the pulse generation circuit unit including a plurality of pulse generation circuits corresponding to respective operating frequencies, a clock control circuit unit which selectively activates a part of the pulse generation circuit in the pulse generation circuit unit, the clock control circuit including a plurality of logic circuits corresponding to the plurality of scan chains, respectively, and a clock control signal generation unit which generates a clock control signal to control the clock control circuit unit, based on the scan clock signal.
Takizawa (US 6275057 B1) teaches, A semiconductor test system having a high repetition rate and small jitter clock generator for supplying the clock signal to a device under test (DUT). The semiconductor test system includes a clock generator for generating a reference clock signal, a frame processor for producing a clock signal of predetermined waveform based on the reference clock signal from the clock generator, a phase lock loop (PLL) circuit for generating a clock signal based on the clock signal from the frame processor where the frequency generated by the PLL circuit is higher than that of the clock signal from the frame processor, and a driver for directly receiving the clock signal from the PLL circuit to apply the clock signal to the DUT with a predetermined amplitude.
Hayashi et al (US 5663668 A) teaches, In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different. Thus, clock skews between the plurality of internal clock signals can be reduced and the phase of the internal clock signal and the phase of the external clock signal can be synchronized.
Cited prior art neither individually nor in combination, fails to teach, anticipate or render obvious, “A semiconductor device comprising: a plurality of reception circuit blocks, each individually receiving a data signal, performing predetermined signal processing for the received data signal, and receiving a test mode signal for instructing a normal operation or a test operation, wherein each of the plurality of reception circuit blocks includes: a phase-locked loop (PLL) circuit generating a clock signal phase-synchronized with a data signal received by itself, a first selector selecting, based on the test mode signal, among the plurality of reception circuit blocks, one of the clock signal generated by the PLL circuit of a different reception circuit block other than a reception circuit block of itself and the clock signal generated by the PLL circuit of the reception circuit block of itself, and a signal processing circuit performing the predetermined signal processing in synchronization with the clock signal selected by the first selector” (as recited in the independent claim 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURESH RAJAPUTRA whose telephone number is (571) 270-0477. The examiner can normally be reached between 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached on 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SURESH K RAJAPUTRA/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 12/31/2025