DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgment has been made to the amendment received on 07/07/2026 Claims 1-6 and 9-11 are pending. Claims 7 and 8 are cancelled. Claim 11 is new claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al (US20100289283A1) in view of Tanaka et al (US20130095613A1).
Re claim 1 Watanabe teach a semiconductor manufacturing apparatus (pick up apparatus, fig 1-6) [0038] that strips semiconductor chips (13, fig 6) [0036] from a dicing sheet (31, fig 6) [0036] on one surface of which an approximately circular wafer (fig 2) including the semiconductor chips (13) is attached, the semiconductor chips being obtained by dividing the wafer (1, fig 1) [0038] into small pieces through dicing, the semiconductor manufacturing apparatus comprising:
a stage (30, fig 6) [0057] which the wafer (1) is disposed through the dicing sheet (31, fig 6) [0057], the stage (30, fig 6) [0057] including a plurality of protrusions (35 and 36, fig 6) [0057] supporting the wafer;
a dicing sheet holder (51, fig 6) [0083] holding the dicing sheet (3, fig 6) [0083]; and a gas evacuation device (4, fig [0058] evacuating gases from a space (37, fig 6) [0058]
between the stage (30, fig 6) and the dicing sheet (31. Fig 6),
wherein the plurality of protrusions (35 and 36, fig 6) [0057] include a plurality of first protrusions (36, fig 6) [0057] and an end disposed on a center portion (middle portion, fig 6) that is an approximately circular region in a center of the stage (center of 30, fig 6) [0057] in a plan view, and at least one second protrusion (35, fig 1, 6) [0057] without any tapered portion (see fig 6) which includes an end (corners of 35, fig 1, 6) disposed on a perimeter portion (left and right ends, fig 6) surrounding the center portion (middle portion, fig 6) in the plan view.
Watanabe does not teach first protrusions each including a tapered portion that is tapered in a cross-sectional view.
Tanaka teaches first protrusions (middle 22, fig. 7) [0056] each including a tapered portion (truncated-pyramid, fig 7) [0069] that is tapered in a cross-sectional view (fig 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Watanabe into the structure of Tanaka to include first protrusions each including a tapered portion that is tapered in a cross-sectional view as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Tanaka in the above manner for the purpose of enhancing the performance and reducing the cost of the device [0004].
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Watanabe and Tanaka does not explicitly teach outer peripheral edges of the wafer are approximately circular and exclude orientation flats include a size of 100 mm, 150 mm, 200 mm, 300 mm, and 450 mm,
for the size of 100 mm, a first distance that is a distance between the center of the center portion and the end of one of the first protrusions that is most far from the center of the center portion in the plan view is 45 ± 2 mm and a second distance that is a distance between the center of the center portion and an edge of the at least one second protrusion which is most far from the center of the center portion in the plan view is any one of 50 mm or longer,
for the size of 150 mm, the first distance is 70 ± 2 mm and the second distance is 75 mm or longer,
for the size of 200 mm, the first distance is , 95 ± 2 mm and the second distance is 100 mm or longer,
for the size of 300 mm, the first distance is 145 ± 2 mm and the second distance is 150 mm or longer, and
for the size of 450 mm, the first distance is 220 ± 2 mm and the second distance is 225 mm or longer.
Watanabe does teach “an outer side diameter of the jig base 30 is almost equivalent to or larger than that of a semiconductor wafer. In the case in which the jig base 30 has an outside diameter that can correspond to the maximum diameter of a standardized size of a semiconductor wafer (for instance 300 mm diameter), the jig base 30 can be applied to all of semiconductor wafers having a diameter smaller than the maximum diameter of a standardized size.” and “an interval between the protrusions (a center-to-center distance of the protrusions) is in the range of 0.2 to 2.0 mm.”. [0060].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Watanabe to include outer peripheral edges of the wafer are approximately circular and exclude orientation flats include a size of 100 mm, 150 mm, 200 mm, 300 mm, and 450 mm,
for the size of 100 mm, a first distance that is a distance between the center of the center portion and the end of one of the first protrusions that is most far from the center of the center portion in the plan view is 45 ± 2 mm and a second distance that is a distance between the center of the center portion and an edge of the at least one second protrusion which is most far from the center of the center portion in the plan view is any one of 50 mm or longer,
for the size of 150 mm, the first distance is 70 ± 2 mm and the second distance is 75 mm or longer,
for the size of 200 mm, the first distance is , 95 ± 2 mm and the second distance is 100 mm or longer,
for the size of 300 mm, the first distance is 145 ± 2 mm and the second distance is 150 mm or longer, and
for the size of 450 mm, the first distance is 220 ± 2 mm and the second distance is 225 mm or longer as claimed.
The ordinary artisan would have been motivated to modify Watanabe and Tanaka in the above manner for the purpose of preventing a displacement and a dropout of a chip [0059].
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) and it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical See for example, in re Ross, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart , 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); MPEP 2144.04.
Re claim 2 Watanabe in view of Tanaka teach the semiconductor manufacturing apparatus according to claim 1, wherein the at least one second protrusion (35, fig 2) [0057] comprises a second protrusion (left 35, fig 6) [0057] that is ring-shaped (see fig 2) and continuous around the center portion in the plan view (continuous around 36, fig 2, 6) [0057].
Re claim 5 Watanabe in view of Tanaka the semiconductor manufacturing apparatus according to claim 1, wherein a pitch between the ends of adjacent two of the first protrusions is 2 mm or less (a center-to-center distance of the protrusions, 0.2 to 2.0 mm fig 6) [Watanabe, 0061].
Re claim 6 Watanabe in view of Tanaka teach the semiconductor manufacturing apparatus according to claim 1, wherein the semiconductor chips (13, fig 3) [Watanabe 0072] are disposed in a center region of the wafer (1, fig 3) [Watanabe, 0072], unnecessary chips that are not the semiconductor chips and are small pieces are disposed in a perimeter region (non-square end pieces, see fig 3) surrounding the center region (center of wafer 1), and the end of at least one of the first protrusions (36, fig 6) overlaps the semiconductor chips (13, fig 6) and the end of the at least one second protrusion overlaps the unnecessary chips in the plan view when the wafer is disposed on the stage. (Since the outer peripheral portion of the semiconductor wafer includes unnecessary chips, it is obvious that the unnecessary chips are arranged on the sidewall.
Re claim 10 Watanabe in view of Tanaka teach the semiconductor manufacturing apparatus according to claim 1, comprising a pick-up device (70, fig 6) [Watanabe, 0086] picking up each of the semiconductor chips from the stage. (see fig 6) [Watanabe, 0086].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe modified by Tanaka as applied to claim 1 and further in view of Tanaka Yoko et al (JP5923876B2).
Re claims 3 and 4 Watanabe in view of Tanaka teach the semiconductor manufacturing
apparatus according to claim 1,
Watanabe and Tanaka do not teach the at least one second protrusion comprises a plurality
of second protrusions that are not continuous in the plan view and a length of a gap between adjacent two of the second protrusions is 1 mm or less.
Watanabe and Tanaka do not teach the at least one second protrusion (23 of 21, fig 2)
[0058] comprises a plurality of second protrusions (plurality of 23in 21, fig 2) that are not continuous in the plan view (fig 2) and a length (t1, fig 2) [0055] of a gap (gap between 21a, fig
1) [0058] between adjacent two of the second protrusions (23 in 21) is 1 mm or less [0055].
It would have been obvious to one ordinary skill in the art before the effective filing date
of the claimed invention to incorporate the teaching taught by Tanaka Yoko into the structure of
Watanabe and Tanaka to include the at least one second protrusion comprises a plurality of second
protrusions that are not continuous in the plan view and a length of a gap between adjacent two
of the second protrusions is 1 mm or less as claimed.
The ordinary artisan would have been motivated to modify Watanabe and Tanaka based
on the teaching of Tanaka Yoko in the above manner in order to avoid problems such as scattering
of semiconductor chips separated by dicing [0006].
Notwithstanding, one ordinary skill in the art would have been led to the recited dimensions
through routine experimentation and optimization. Applicant has not disclosed that the dimensions
are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical,
and it appears prima facie that the process would possess utility using another dimension. Indeed,
it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that
the limitations are for a particular unobvious purpose, produce an unexpected result, or are
otherwise critical See for example, in re Ross, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re
Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); MPEP 2144.04.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe modified
by Tanaka as applied to claim 1, and further in view of Kurosawa et al (JP2013110244A).
Re claim 9 Watanabe in view of Tanaka teaches teach the semiconductor manufacturing
apparatus according to claim 1,
Watanabe and Tanaka do not teach the dicing sheet holder has a function of extending the
dicing sheet in a direction from the center of the stage toward an outer peripheral edge of the stage.
Kurosawa does teach the dicing sheet holder (71, fig 4) [0026] has a function of extending
the dicing sheet (DS, fig 4) [0025] in a direction (horizontal) from the center of the stage (21, fig
4) [toward an outer peripheral edge of the stage (21, fig 4) [0061] (the expanding means 7 lowers
the contact portions 72 and 74 by driving the linear motion motor 71. Thereby, the dicing sheet
DS is pulled, and the gap between the chips CP is expanded,) [0029].
It would have been obvious to one ordinary skill in the art before the effective filing date
of the claimed invention to incorporate the teaching taught by Kurosawa into the structure of
Watanabe to include the dicing sheet holder has a function of extending the dicing sheet in a
direction from the center of the stage toward an outer peripheral edge of the stage as claimed.
The ordinary artisan would have been motivated to modify Kurosawa based on the teaching
of Watanabe and Tanaka in the above manner for the purpose of improving the manufacturing
operation efficiency of the semiconductor product using the chips CP. [0031]
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Tanaka and Yoshida et al (US 20180197825 A1).
Re claim 11 Watanabe teach a semiconductor manufacturing apparatus (pick up apparatus, fig 1-6) [0038] that strips semiconductor chips (13, fig 6) [0036] from a dicing sheet (31, fig 6) on one surface of which an approximately circular wafer (circular shape wafer see fig 2) including the semiconductor chips(13,fig 6) is attached, the semiconductor chips (13) being obtained by dividing the wafer (1, fig 1) into small pieces through dicing, the semiconductor manufacturing apparatus comprising:
a stage (30, fig 6) [0057] on which the wafer (1) is disposed through the dicing sheet (30, fig 6) [0057], the stage (30, fig 6) including a plurality of protrusions (35 and 36, fig 6) [0057] supporting the wafer (1, fig 6);
a dicing sheet holder (51, fig 6) [0083] holding the dicing sheet (3, fig 6) [0083]; and
a gas evacuation device (4, fig 6) [0058] evacuating gases from a space (37, fig 6) [0058] between the stage (30, fig 6) and the dicing sheet (31, fig 6),
wherein the plurality of protrusions (35 and 36, fig 6) [0057] include a plurality of first protrusions (36, fig 6) [0057 and an end disposed on a center portion (middle portion fig 6) that is an approximately circular region in a center of the stage (center of 30, fig 6) [0057] in a plan view, and at least one second protrusion (35, fig 1, 6) [0057] without any tapered portion (fig 6) which includes an end (corner of 35, fig 1, 6) disposed on a perimeter portion (left/right portion fig 6) surrounding the center portion (middle portion, fig 6) in the plan view,
Watanable does not tech first protrusions each including a tapered portion that is tapered in cross-section view.
Tanaka tach first protrusions (middle 22, fig. 7) [0056] each including a tapered portion (truncated-pyramid, fig 7) [0069] that is tapered in a cross-sectional view (fig 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Watanabe into the structure of Tanaka to include first protrusions each including a tapered portion that is tapered in a cross- sectional view as claimed.
The ordinary artisan would have been motivated to modify Watanabe based on the teaching of Tanaka in the above manner for the purpose of enhancing the performance and reducing the cost of the device [0004].
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Watanabe and Tanaka do not teach the semiconductor chips include a semiconductor chip to be a product and an unnecessary chip that is not to be a product, the center portion corresponds to a position of the semiconductor chip to be a product, and the perimeter portion corresponds to a position of the unnecessary chip.
Yoshida teaches fig 2 the semiconductor chips (SC2/SC1, fig 2) [ 0050] a semiconductor chip (SC1, fig 2) [0050] to be a product (product chip) and an unnecessary chip ( SC2, pseudo chip) that is not to be a product [0050], the center portion (center portion fig 2) corresponds to a position of the semiconductor chip to be a product (SC1), and the perimeter portion (dummy region ) [0050] corresponds to a position of the unnecessary chip (pseudo chips) [0096].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoshida into the structure of Watanabe and Tanaka to include the semiconductor chips include a semiconductor chip to be a product and an unnecessary chip that is not to be a product, the center portion corresponds to a position of the semiconductor chip to be a product, and the perimeter portion corresponds to a position of the unnecessary chip as claimed.
The ordinary artisan would have been motivated to modify Watanabe and Tanaka based on the teaching of Yoshida in the above manner for the purpose of improving the manufacturing yield of a semiconductor device [0009].
Response to Arguments
Applicant’s arguments with respect to claims 1-6 and 9-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takeda et al (JP2010027950A) teaches a method of manufacturing a semiconductor device capable of improving a yield and reliability of a product.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/22/26
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