DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 and 14-20 in the reply filed on 9/3/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/18/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2024/0304619) in view of Tsai (US 2025/0081512)
Regarding claim 1.
Xu teaches
A semiconductor structure (fig 1,5N:100; [para 0030]), comprising: a back-end-of-line (BEOL) (fig 5N:510; [para 0069]) on a first side (fig 3:305; [para 0061]) of a front-end-of-line (FEOL) (fig 5N:520; [para 0069]);
a backside power delivery network (BSPDN) (fig 5n:545; [para 0078]) on a second side (fig 5f:501; [para 0069]) of the FEOL (fig 5n:520; [para 0069]);
a backside single diffusion break (BSDB) (fig 5L:534,539; [para 0077]) tapered from the BSPDN (fig 5n:545; [para 0078]) to the BEOL (fig 5N:510; [para 0069]);
Xu does not teach a double diffusion break.
Tsai teaches:
A semiconductor structure (fig 14:200; [para 0013]), comprising: a first side of a front-end-of-line (FEOL) (fig 4:210; [para 0016]);
a single diffusion break (SDB) (fig 14:230; [para 0027]);
and a double diffusion break (DDB) (fig 18:2302; [para 0039])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the structure to comprises a backside single diffusion break and a backside double diffusion break, the combination of which is a backside single diffusion break (BSDB) tapered from the BSPDN to the BEOL; and a backside double diffusion break (BDDB) tapered from the BSPDN to the BEOL,because using a single diffusion break will conserve area and using a double diffusion break where necessary to reduce stress and increase separation.
Claim(s) 4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2024/0304619) in view of Tsai (US 2025/0081512) as applied to claim 1 and further in view of Xie (US 2024/0072134)
Regarding claim 4.
Xu in view of Tsai teaches the semiconductor structure of claim 1, further
Xu teaches:
a first source/drain (S/D) (fig 5n:527; [para 0070]) directly adjacent to the BSDB (fig 5n:534,539; [para 0077]);
Xu in view of Tsai does not teach a placeholder.
Xie teaches:
a placeholder (fig 20c:902; [para 0088]) directly beneath the first S/D (fig 20c:1000p; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a placeholder beneath the source/drain in order to facilitate the formation of backside contacts to the source drain structures (Xie paragraph 9) thereby enabling the fabrication of more closely spaced transistors (Xie paragraph 11).
Regarding claim 7.
Xu in view of Tsai in view of Xie teaches the semiconductor structure of claim 4, further
Tsai teaches:
a gate-and-S/D cut dielectric (fig 18:270; [para 0035]) between the [source/drain feature] (fig 19:236; [para 0021]) and the BDDB (fig 19:2302; [para 0039]).
Xie teaches:
a backside gate-and-S/D cut dielectric (fig 20a:1016; [para 0066]) between the placeholder (fig 20a:902; [para 0056]) and the [diffusion] (fig 20a:1000p; [para 0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a backside gate-and-S/D cut dielectric between the placeholder and the BDDB in order to sever the gate structure thereby isolating separate transistor structures into multiple transistor enabling the fabrication of more transistors with a smaller spacing and a finer pitch (Xia paragraph 11).
Claim(s) 1, 2, and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2024/0304619) in view of Li (US 2020/0343144)
Regarding claim 1.
Xu teaches:
A semiconductor structure (fig 1,5N:100; [para 0030]), comprising: a back-end-of-line (BEOL) (fig 5N:510; [para 0069]) on a first side (fig 3:305; [para 0061]) of a front-end-of-line (FEOL) (fig 5N:520; [para 0069]);
a backside power delivery network (BSPDN) (fig 5n:545; [para 0078]) on a second side (fig 5f:501; [para 0069]) of the FEOL (fig 5n:520; [para 0069]);
a backside single diffusion break (BSDB) (fig 5L:534,539; [para 0077]) tapered from the BSPDN (fig 5n:545; [para 0078]) to the BEOL (fig 5N:510; [para 0069]);
Xu does not teach a double diffusion break.
Li teaches:
A semiconductor structure (fig 1:100; [para 0030]), comprising: a first side of a front-end-of-line (FEOL);
a single diffusion break (SDB) (fig 1:150; [para 0030]);
and a double diffusion break (DDB) (fig 1:152; [para 0030])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the structure to comprises a backside single diffusion break and a backside double diffusion break, the combination of which is a backside single diffusion break (BSDB) tapered from the BSPDN to the BEOL; and a backside double diffusion break (BDDB) tapered from the BSPDN to the BEOL,because using a single diffusion break will conserve area and using a double diffusion break where necessary to reduce stress and increase separation.
Regarding claim 2.
Xu in view of Li teaches the semiconductor structure of claim 1, further
Xu teaches:
a backside diffusion break (BDB) (fig 5L:534,539; [para 0077])
Li teaches:
wherein the SDB (fig 1:150; [para 0030]) is located on a first row (fig 1:cell b; [para 0030])and the DDB (fig 1:152; [para 0030]) is located on second row (fig 1:cell a; [para 0030]) adjacent to the first row (fig 1:cell b; [para 0030]).
Regarding claim 3
Xu in view of Li teaches the semiconductor structure of claim 2, further
Li teaches:
the first row (fig 1:cell b; [para 0030]) comprises an NFET semiconductor (fig 1,2a; [para 0031]) and the second row (fig 1:cell a; [para 0030]) comprises a PFET semiconductor (fig 1,2a; [para 0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use nfet and pfet in order to form cmos
Claim(s) 4, 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2024/0304619) in view of Li (US 2020/0343144) as applied to claim 1 and further in view of Xie (US 2024/0072134)
Regarding claim 4.
Xu in view of Li teaches the semiconductor structure of claim 1, further
Xu teaches:
a first source/drain (S/D) (fig 5n:527; [para 0070]) directly adjacent to the BSDB (fig 5n:534,539; [para 0077]);
Xu in view of Li does not teach a placeholder.
Xie teaches:
a placeholder (fig 20c:902; [para 0088]) directly beneath the first S/D (fig 20c:1000p; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a placeholder beneath the source drain in order to facilitate the formation of backside contacts to the source drain structures (paragraph 9) thereby enabling the fabrication of more closely spaced transistors (Xie paragraph 11).
Regarding claim 5.
Xu in view of Li in view of Xie teaches the semiconductor structure of claim 4, further
Xu teaches:
a second S/D (fig 5n:527; [para 0070]) directly adjacent to the BSDB (fig 5l,5n:534,539; [para 0077]) on an opposite side of the first S/D (fig 5n:527; [para 0070]);
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Xie teaches:
a second S/D (fig 20c:1000p; [para 0088]);
and a backside S/D contact (fig 20c:1902; [para 0088]) electrically connected between the second S/D (fig 20c:1000p; [para 0088]) and the BSPDN (fig 20c:2004; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a contact between the backside power network and the S/D in order to convey power from the network to the drain through the shortest route.
Regarding claim 6.
Xu in view of Li in view of Xie teaches the semiconductor structure of claim 5, further
Xu teaches:
the BSDB (fig 1:150; [para 0030]) is directly between (fig 1; [para 0046]) .
[a first region (fig 1:130b; [para 0046]) and a second region (fig 1:130c; [para 0046])]
Xie teaches:
the placeholder (fig 20c:902; [para 0088])and the backside S/D contact (fig 20c:1902; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the BSDB structure directly between the placeholder and the backside S/D contact in order to separate a PMOS from an NMOS (Xu paragraph 49) transistor and thus enable denser placement of transistors without current leakage and to properly align the backside power supply connections to the individual devices (Xie paragraph 4) in order to reduce the front side area occupied by power supplying connections.
Claim(s) 14, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2020/0343144) in view of Xu (US 2024/0304619)
Regarding claim 14.
Li teaches:
A semiconductor structure (fig 1:100; [para 0030]), comprising: a single diffusion break (SDB) (fig 1:150; [para 0030]) located on a first row (fig 1:cell b; [para 0030]) of a front-end-of-line (FEOL) layer of the semiconductor structure (fig 2a:200; [para 0031]);
and a double diffusion break (DDB) (fig 1:152; [para 0030]) located on a second row of the FEOL layer (fig 2a:200; [para 0031]), wherein the second row (fig 1:cell a; [para 0030]) is directly adjacent to the first row (fig 1:cell b; [para 0030]).
Li does not teach a backside diffusion break.
Xu teaches:
A semiconductor structure (fig 1,5N:100; [para 0030]), comprising: a front-end-of-line (FEOL) (fig 5N:520; [para 0069]);
a backside diffusion break (BSDB) (fig 5L:534,539; [para 0077])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the structure to single diffusion break to be a backside single diffusion break and for the double diffusion break to be a backside double diffusion break in order to conserve frontside area (paragraph 14 and 15)
Regarding claim 15.
Li in view of Xu teaches the semiconductor structure of claim 14, further:
Li teaches:
the [SBD] (fig 1:150; [para 0030]) and the [DDB] (fig 1:152; [para 0030]) .
Xu teaches
[backside diffusion break] (fig 5L:534,539; [para 0077]) are tapered from a backside (fig 5L,5N:501; [para 0069]) of the FEOL (fig 5N:520; [para 0069]) to a frontside (fig 5N).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the structure the single diffusion break and the double diffusion break, as taught by Li, to comprise backside diffusion breaks that are tapered from a backside of the FEOL to the frontside in order increase the width of and separation provided by the break, reduce current leakage and reduce the amount of frontside area occupied by diffusion break(paragraph 14 and 15)
Regarding claim 16.
Li in view of Xu teaches the semiconductor structure of claim 14, further:
Li teaches:
the first row comprises (fig 1:cell b; [para 0030])an NFET semiconductor (fig 1,2a; [para 0031]) and the second row comprises (fig 1:cell a; [para 0030]) a PFET semiconductor (fig 1,2a; [para 0031])
Claim(s) 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2020/0343144) in view of Xu (US 2024/0304619) as applied to claim 14 and further in view of Xie (US 2024/0072134)
Regarding claim 17.
Li in view of Xu teaches the semiconductor structure of claim 14, further
Xu teaches:
a first source/drain (S/D) (fig 5n:527; [para 0077])directly adjacent to the BSDB (fig 5L:534,539; [para 0077]);
Li in view of Xu does not teach a placeholder.
Xie teaches:
a placeholder (fig 20c:902; [para 0088]) directly beneath the first S/D (fig 20c:1000p; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a placeholder directly beneath the source drain in order to facilitate the formation of backside contacts to the source drain structures (Xie paragraph 9) and thereby facilitate reducing the space between transistors (Xie paragraph 3).
Regarding claim 18.
Li in view of Xu in view Xie teaches the semiconductor structure of claim 17, further
Xu teaches:
a second S/D (fig 5n:527; [para 0070]) directly adjacent to the BSDB (fig 5l,5n:534,539; [para 0077]) on an opposite side of the first S/D (fig 5n:527; [para 0070]);
the second S/D (fig 5n:537; [para 0070]) and a backside power delivery network (BSPDN) (fig 5n:545; [para 0078]).
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Xie teaches:
A second S/D (fig 20c:1000p; [para 0088])
and a backside S/D contact (fig 20c:1902; [para 0088]) electrically connected between the second S/D (fig 20c:1000p; [para 0088]) and a backside power delivery network (BSPDN) (fig 20c:2004; [para 0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a backside S/D contact between the backside power network and the S/D in order to convey power from the network to the drain the shortest route.
Regarding claim 19.
Li in view of Xu in view Xie teaches the semiconductor structure of claim 18, further
Xu teaches:
the BSDB (fig 1:150; [para 0030])is directly between (fig 1; [para 0046])[a first region (fig 1:130b; [para 0046]) and a second region (fig 1:130c; [para 0046])
Xie teaches:
The placeholder (fig 20c:902; [para 0088])and the backside S/D contact (fig 20c:1902; [para 0088])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the BSDB structure between a placeholder and a S/D contact in order to separate a PMOS from an NMOS (Xu paragraph 49) transistor and thus enable denser placement of transistors without current leakage and to properly align the backside power supply connections to the individual devices (Xie paragraph 4) in order to reduce the front side area occupied by power supplying connections.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2020/0343144) in view of Xu (US 2024/0304619) in view of Xie (US 2024/0072134) as applied to claim 17 and further in view of Tsai (US 2025/0081512)
Regarding claim 20.
Li in view of Xu in view of Xie teaches the semiconductor structure of claim 17, further
Xie teaches:
a backside gate-and-S/D cut dielectric (fig 20a:1016; [para 0066])between the placeholder (fig 20a:902; [para 0056]) [diffusion] (fig 20a:1000p; [para 0060]).
Tsai teaches:
a gate-and-S/D cut dielectric (fig 19:270; [para 0035])between the [diffusion] (fig 19:236; [para 0021]) and the DDB (fig 19:2302; [para 0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a backside gate-and-S/D cut dielectric between the placeholder and the BDDB in order to sever the gate conductor thereby forming a plurality of closely spaced transistors, improving performance and yield (Tsai paragraph 12).
Conclusion
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/D.J.G/ Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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