DETAILED ACTION
This action is in response to the application filed on 3/18/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore the gate of the fourth transistor being coupled to the gate, source, and drain terminal of the third transistor and the source and drain terminal of fourth transistor being coupled to a second source and drain terminal of the third transistor or claim 4, the source/drain of the first transistor being configured to receive the output voltage of the converter of claims 7 and 10, and the source and drain terminal of the first transistor being coupled to a source and drain terminal of the fourth transistor and the source and drain terminal of the second transistor being coupled to a source and drain terminal of the third transistor and a gate terminal of the fourth transistor or claim 12, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 16 and 18 are objected to because of the following informalities: Regarding claim 16, the limitation “a sensing circuit configured modify or maintain a count of the counter” should be written as “a sensing circuit configured to modify or maintain a count of the counter. Regarding claim 18, the limitation “a sensing circuit configured modify or maintain a count of the counter” should be written as “a sensing circuit configured to modify or maintain a count of the counter. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 6-10 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 4, it’s not clear as to how the gate of the fourth transistor is coupled to the gate, source, and drain terminal of the third transistor. Furthermore, it’s not clear as to how the source and drain terminal of fourth transistor is coupled to a second source and drain terminal of the third transistor. Regarding claim 6, the limitation “the first transistor” lacks proper antecedent basis and should be written as “a first transistor”. Regarding claim 7, it’s not clear as to how the source and drain of the first transistor is configured to receive an output voltage of the converter. Dependent claims 8-9 inherits the deficiencies of dependent claim 7 and are therefore also rejected under 35 U.S.C. 112 (b). Regarding claim 10, it’s not clear as to how the source and drain of the first transistor is configured to receive an output voltage of the converter. Regarding claim 12, it’s not clear as to how the source and drain terminal of the first transistor is coupled to a source and drain terminal of the fourth transistor. Furthermore, it’s not clear as to how the source and drain terminal of the second transistor is coupled to a source and drain terminal of the third transistor and a gate terminal of the fourth transistor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 2006/0007713) in view of Chen et al. (US Patent 10075085). Regarding claim 1, Brown discloses (see fig. 1) a circuit for controlling dead-time of a converter, the circuit comprising: a counter (23/25) configured to modify or maintain a delay time of a delay cell (operation of 23/25 controlling the operation of delay cell 16); and a sensing circuit (15) configured to drive the counter (output from 15 used in controlling 23/25). Brown does not disclose a counter configured to minimize or eliminate the dead time of the converter. Chen et al. discloses (see fig. 1 and 4) a counter (412/420) configured to minimize or eliminate a dead time of a converter (operation of counter controlling the 414/416 and 422/424 to reduce a dead-time). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Brown to include the features of Chen et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 2, Brown discloses that the sensing circuit (15) is further configured to either modify or maintain a count of the counter (operation of 15 controlling the operation of 23/25). Regarding claim 15, Brown discloses (see fig. 1) circuit comprising: one or more delay cells (delay cell 16); and a counter (23/25) coupled to the one or more delay cells (connection to 16) and configured to modify or maintain a delay time of the one or more delay cells (operation of 23/25 controlling the operation of delay cell 16). Brown does not disclose a counter configured to minimize or eliminate the dead time of the converter. Chen et al. discloses (see fig. 1 and 4) a counter (412/420) configured to minimize or eliminate a dead time of a converter (operation of counter controlling the 414/416 and 422/424 to reduce a dead-time). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Brown to include the features of Chen et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 2006/0007713) in view of Chen et al. (US Patent 10075085) and Guan et al. (US Patent 8542500). Regarding claim 5, Brown does not disclose a capacitor coupled between the sensing circuit and ground; and a switch coupled in parallel with the capacitor. Guan et al. discloses (see fig. 3) a capacitor (C11) coupled between a sensing circuit (332) and ground (ground); and a switch (M11) coupled in parallel with the capacitor (parallel connection between gate and source). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Brown to include the features of Guan et al. because it allows for a specific design choice, which can provide a specific/desired type of operation, thus reducing operational variances and increasing operational efficiencies.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 2006/0007713) in view of Goodfellow et al. (US Patent 6559684). Regarding claim 11, Brown discloses (see fig. 1) a method comprising: determining, via a circuit, a first current (operation of 15); determining a count based on the first current (operation of 15 controlling counters 23/25); providing the count to a delay cell (output from counter to delay cell 16). Brown does not disclose providing a second current to a first transistor, wherein the first transistor is coupled to the circuit and has a gate terminal coupled to a reference voltage. Goodfellow et al. discloses (see fig. 3) a second current to a first transistor (current through transistor 302), wherein the first transistor is coupled to a circuit (connection to 308/306) and has a gate terminal coupled to a reference voltage (gate of 302 connected to ground). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Brown to include the features of Goodfellow et al. because it allows for a specific design choice, which can provide a specific/desired type of operation, thus reducing operational variances and increasing operational efficiencies.
Allowable Subject Matter
Claims 3, 13-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Petrina et al. (US Patent 12155389) discloses methods and apparatus for adjusting a dead time. Brown et al. (US 2012/0105034) discloses controlling a dead time of a switching voltage regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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