Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ponnathota et al. (USPAPN 2013/0311792).
With respect to claim 8, a semiconductor device (Fig. 1, operational details disclose in Figs. 2 and 10B) comprising:
an integrated circuit (integrated circuit associated with the processor 105 of Fig. 1, see paragraphs 0065 and 0079) including:
an integrated circuit die (die associated with the integrated circuit/chip. Integrated circuits are structed on a die/substrate);
a plurality of first voltage sensors (125a-125n, the above monitors sense conditions within the processor and a voltage is controlled responsive to the sensing of the monitors. Thus, the monitors are voltage sensors, since they sense a voltage adjustment level that is required to maintain regulation of the power voltage, see paragraph 0067) each configured to detect a voltage at a distinct location of the integrated circuit die (see paragraph 0067 “…selecting monitors that are close to the critical path…” of paragraph 0067. Thus, the monitors are placed at distinct locations to provide the voltage sensing at the distinct location);
a programmable configurator preset with weighing factors assigned to the voltages detected by the first voltage sensors (the LUT 140 of controller 110 assigns weights to the monitors, see paragraph 0109 and 230 with 235 of Fig. 2) ; and
a digital voltage offset controller (DVOC) (each 1007 of Fig. 10B) configured to multiply the voltages detected by the first voltage sensors (output of 125a-125n) with the weighing factors (output of 1010a-1010n) and to generate a first digital sense voltage (one of 1015 and 1020 which are dependent upon the DVOC output).
With respect to claim 9, the semiconductor device of claim 8, further comprising a digital voltage regulator (114/115 of Fig. 1/115 of Fig. 10B) configured to receive the first digital sense voltage (via 110 of Figs. 1/10B) and to generate a regulated output voltage (output of 115, see 117 of Fig. 1), wherein the integrated circuit is configured to receive the regulated output voltage (105 receives 117).
With respect to claim 15, (Currently amended) A semiconductor device comprising:
a semiconductor device (Fig. 1, operational details disclose in Figs. 2 and 10B) comprising:
an integrated circuit (integrated circuit associated with the processor 105 of Fig. 1, see paragraphs 0065 and 0079) including:
an integrated circuit die (die associated with the integrated circuit/chip. Integrated circuits are structed on a die/substrate);
a plurality of first voltage sensors (125a-125n, the above monitors sense conditions within the processor and a voltage is controlled responsive to the sensing of the monitors. Thus, the monitors are voltage sensors, since they sense a voltage adjustment level that is required to maintain regulation of the power voltage, see paragraph 0067) each configured to detect a voltage at a distinct location of the integrated circuit die (see paragraph 0067 “…selecting monitors that are close to the critical path…” of paragraph 0067. Thus, the monitors are placed at distinct locations to provide the voltage sensing at the distinct location);
a thermal sensor configured to detect a temperature of the integrated circuit (130 of Fig. 1); and
a digital voltage offset controller (DVOC) (LUT 130) configured to adjust the voltage detected by a selected one of the voltage sensors based on the temperature detected by the thermal sensor (the 130 configures the monitors, i.e., adjusts the detected voltage of the monitors, according to the sampled temperature of 130, see 225, 230, 235 and 240 of Fig. 2. Furthermore, at least one of the monitors is selected thus the configuration happens to at least a selected one of the monitors, see paragraphs 0067 and 0082) and to generate a first digital sense voltage based on the adjusted voltage (the digital sense voltage is adjusted according to the configuration of the monitors, see 235, 240, 245 and 250 of Fig. 2, see also paras 0080, 0083 and 102-109).
Claim 16 is rejected for essentially the same reasons as claim 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ponnathota et al., alone, or Ponnathota et al. in view of Garg et al. (USPN 12,093,100)
With respect to claim 1, a semiconductor device (Fig. 1, operational details disclose in Figs. 2 and 10B) comprising:
an integrated circuit (integrated circuit associated with the processor 105 of Fig. 1, see paragraphs 0065 and 0079) including:
an integrated circuit die (die associated with the integrated circuit/chip. Integrated circuits are structed on a die/substrate);
a plurality of first voltage sensors (125a-125n, the above monitors sense conditions within the processor and a voltage is controlled responsive to the sensing of the monitors. Thus, the monitors are voltage sensors, since they sense a voltage adjustment level that is required to maintain regulation of the power voltage, see paragraph 0067), wherein multiple ones of the first voltage sensors are each configured to detect a voltage at a distinct location of the integrated circuit die (see paragraph 0067 “…selecting monitors that are close to the critical path…” of paragraph 0067, see also paragraph 0079. Thus, the monitors are placed at distinct locations to provide the voltage sensing at the distinct location);
a digital voltage offset controller (DVOC) configured to generate a first digital sense voltage based on the voltage detected by a selected one of the first voltage sensors (110 generating the sense signal of bus master/digital signal to 115 according to which of the monitors of 125a-125n are selected/ignored, see paragraph 0067)
Ponnathota et al. merely discloses a single processor/integrated circuit die. Thus, Ponnathota et al. fails to disclose multiple integrated circuit dies and thus fails to disclose
“a plurality of integrated circuit dies” and “wherein multiple ones of the first voltage sensors are each configured to detect a voltage at a distinct location of one of the integrated circuit dies”.
However, it would have been obvious to construct the processor circuit from multiple integrated circuit dies, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. One would have been motivated to do so for the purpose of increasing the processing power of the processing circuit (i.e., using multiple processors allows for increased processing capabilities/power).
Furthermore/alternatively, the use of multiple interconnected processor dies is well-known as evidenced in Fig. 1B of Garg et al. which discloses multiple processor dies (101_00 to 101_13) that are interconnected and operative together as a processor device.
It would have been obvious to connected multiple processor dies together in the circuit of Ponnathota et al. to operate as a combined processor (i.e., 105) for the purpose of increasing processor capacity.
Claim 2 is rejected for essentially the same reasons as claim 9.
Allowable Subject Matter
Claims 3-7, 10-14 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 8-9 and 15-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849