DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: MONOLITHICALLY INTEGRATED MICROWAVE SEMICONDUCTOR DEVICE STRUCTURE.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on April 30, 2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Piedra (US 2021/0118871 A1) in view of Male (US 2019/0057942 A1).
Claim 1, Piedra discloses a monolithically integrated semiconductor device structure (monolithic microwave integrated circuit (MMIC) 200 is a monolithically integrated semiconductor device structure, hereinafter, monolithically integrated semiconductor device structure 200, [0033], Fig. 2), comprising:
a substrate (substrate 202, [0033], Fig. 2) comprising a transistor region (gate region 210, source region 214, and drain region 218 are a part of a transistor region, hereinafter, transistor region 210/214/218, [0037], Fig. 2); and
a transistor (gate electrical contact 208, the first ohmic contact 212, and the second ohmic contact 216, are a part of a transistor, hereinafter, transistor 212/208/216, [0037], Fig. 2) positioned above the transistor region 210/214/218 (transistor 212/208/216 is positioned above the transistor region 210/214/218, [0037], Fig. 2) comprising at least one first trench (opening 420 is at least one first trench and is filled with a metallic material 428 within a through-substrate via 424, hereinafter, at least one first trench 242, [0042], Figs. 2 and 4) that are arranged in a horizontal direction and extend in a vertical direction (at least one first trench 242 arranged in a horizontal direction and extend in a vertical direction, [0036] and [0042], Figs. 2, 4, and 6), and
wherein the first trench 242 is disposed below a drain of the transistor 212/208/216 (first trench 242 is disposed below drain region 218, wherein drain region 218 includes a second ohmic contact 216 which is a drain of the transistor 212/208/216, hereinafter, drain of the transistor 216, [0037], Fig. 2).
Piedra does not explicitly disclose a transistor comprising at least one first trench and at least one second trench, wherein the second trench is disposed below a non-drain region of the transistor.
However, Male discloses an integrated semiconductor device structure (Male, transformer 548 is an integrated semiconductor device structure, hereinafter, integrated semiconductor device structure 548, [0044], Fig. 5; Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2), comprising:
a substrate (Male, semiconductor substrates 508/508a are a substrate, hereinafter, substrate 508/508a, [0044], Fig. 5; Piedra, substrate 202, [0033], Fig. 2) comprising a transistor region (Male, substrate 508/508a comprises a transistor region, [0019], Figs. 1 and 5; Piedra, transistor region 210/214/218, [0037], Fig. 2); and
a transistor (Male, transistors are included within the transistor region, [0019], Fig. 5; Piedra, transistor 212/208/216, [0037], Fig. 2) positioned above the transistor region (Male, transistors are included within the transistor region, [0019], Fig. 5; Piedra, transistor 212/208/216 is positioned above the transistor region 210/214/218, [0037], Fig. 2) comprising at least one first trench (Male, dielectric filled trenches 522 are at least one first trench, hereinafter, at least one first trench 522, [0046], Fig. 5; Piedra, at least one first trench 242, [0042], Figs. 2 and 4) and at least one second trench (Male, dielectric filled tranches 522a are at least one second trench, hereinafter, at least one second trench 522a, [0047], Fig. 5; Piedra, at least one second trench 208, [0036] and [0089], Figs. 2 and 6) that are arranged in a horizontal direction and extend in a vertical direction (Male, at least one first trench 522 and at least one second trench 522a are arranged in a horizontal direction and extend in a vertical direction, [0046], Fig. 5; Piedra, at least one first trench 242 and at least one second trench 208 are arranged in a horizontal direction and extend in a vertical direction, [0036] and [0042], Figs. 2, 4, and 6),
wherein the first trench is disposed below a drain of the transistor (Male, at least one first trench 522 is disposed below a drain of a transistor included within substrate 508/508a, [0046], Fig. 5; Piedra, first trench 242 is disposed below a drain of the transistor 216, [0037], Fig. 2), and the second trench is disposed below a non-drain region of the transistor (Male, at least one second trench 522a is disposed below a non-drain of a transistor included within substrate 508/508a, [0046], Fig. 5; Piedra, second trench 208 is disposed below a non-drain of the transistor 212, [0037], Fig. 2). The combination to utilize a plurality of dielectric filled trenches penetrating deep into or completely through the underlying substrate in a direction that is normal to the overlying induction coil enables a reduction or prevention in induced eddy currents in the semiconductor substrate, thereby increasing a quality (Q) factor for the induction coil resulting in increased power transfer efficiency and expands the frequency of operation (Male, [004] and [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a plurality of dielectric filled trenches penetrating deep into or completely through the underlying substrate in a direction that is normal to the overlying induction coil enables a reduction or prevention in induced eddy currents in the semiconductor substrate, thereby increasing a quality (Q) factor for the induction coil resulting in increased power transfer efficiency and expands the frequency of operation (Male, [004] and [0033]).
Claim 2, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein the substrate (Male, substrate 508/508a, [0044], Fig. 5; Piedra, substrate 202, [0033], Fig. 2) further comprises a capacitive region (Piedra, substrate 202 further comprises a first plate 220 and second plate 222 of a capacitor, hereinafter, the orthogonal projection in a vertical direction is a capacitive region, hereinafter, capacitive region 220/222_R, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5), the semiconductor device structure further comprises a capacitor, and the capacitor is positioned above the capacitive region (Piedra, monolithically integrated semiconductor device structure 200 further comprises a first plate 220 and second plate 222 of a capacitor, hereinafter, capacitor 220/222, wherein the capacitor 220/222 is positioned above the capacitive region 220/222_R, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5); and
the capacitive region comprises the at least one first trench (Piedra, capacitive region 220/222_R comprises at least one first trench 242 (i.e. overlapping the source region 214), [0037], Fig. 2; Male, at least one first trench 522, [0046], Fig. 5) arranged in the horizontal direction and extend in the vertical direction (Piedra, capacitive region 220/222_R and the at least one first trench 242 is arranged in the horizontal direction and extend in the vertical direction, [0037], Fig. 2; Male, at least one first trench 522 is arranged in the horizontal direction and extend in the vertical direction, [0046], Fig. 5).
Claim 3, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein first dielectric is filled in the first trench (Male, at least one first trench 522 is filled with a replacement dielectric and is a first dielectric, [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 4, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 3.
Piedra/Male discloses wherein the first dielectric comprises a low-k material (Male, first dielectric comprises a low-k material (i.e. benzocyclobutene (BCB)), [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 5, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 4.
Piedra/Male discloses wherein the low-k material comprises at least one of: an inorganic material, an organic material, a porous material or air (Male, low-k material comprises at least one of: an organic material (i.e. benzocyclobutene (BCB)), [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 6, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein second dielectric is filled in the second trench (Male, at least one second trench 522a is filled with a replacement dielectric and is a second dielectric, [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 7, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 6.
Piedra/Male discloses wherein the second dielectric comprises an insulating material (Male, second dielectric comprises an insulating material (i.e. epoxy, polyimide, benzocyclobutene (BCB), ceramic filled polymer), [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 8, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 7.
Piedra/Male discloses wherein the insulating material comprises at least one of: an oxide material, a nitride material, an organic polymer material, a diamond or air (Male, insulating material comprises at least one of: an organic polymer material (i.e. polyimide, benzocyclobutene (BCB)), [0029], Fig. 5; Piedra, first trench 242, [0037], Fig. 2).
Claim 9, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein the substrate is a silicon substrate (Male, substrate 508/508a is a silicon substrate, [0018], Fig. 5; Piedra, substrate 202 is a silicon substrate, [0018], Fig. 2).
Claim 10, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein openings of the first trench and the second trench are disposed on a surface, facing the transistor, of the substrate, and the first trench and the second trench penetrate through the substrate or do not penetrate through the substrate (Male, openings of the trenches 1122 are disposed on a surface, facing the transistor, of the substrate 1108, and the trenches 1122 penetrate through the substrate 1108 or do not penetrate through the substrate 1108, [0079] – [0081], Figs. 11E, 11F, and 11G; Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2).
Claim 13, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein a projection shape of one or both of the first trench and the second trench on a plane where the substrate is located comprises at least one of: a circle, an ellipse, a polygon, a strip or a mesh (Male, a projection shape of one or both of the trenches 321/322/422 (i.e. at least one first trench 522 and the at least one second trench 522a) on a plane where the substrate 508/508a is located comprises at least one of: a polygon (i.e. Fig. 3D, 4C) or a strip (i.e. Fig. 3D), [0046], Fig. 5; Piedra, substrate 202, [0037], Fig. 2).
Claim 14, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein a cross-sectional area of the first trench and/or the second trench increases gradually or is a constant along a direction from the substrate to the transistor (Piedra, a cross-sectional area of the first trench 242 and/or the second trench 208 increases gradually or is a constant along a direction from the substrate 202 to the transistor 212/208/216, Fig. 2; Male, a cross-sectional area of the at least one first trench 522 and/or the at least one second trench 522a increases gradually or is a constant along a direction from the substrate 508/508a to the transistor, Figs. 3E and 5).
Claim 15, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein the substrate 202 further comprises an inductive region (Male, substrate 508/508a further comprise an inductive region overlapping embedded inductor coil 510/510a, [0044], Fig. 5; Piedra, the orthogonal projection of the first additional metallic device 232 and second additional metallic device 238 which may include an inductor, on the underlying substrate 202 and adjacent to the central transistor region 210/214/218 forms an inductor region, hereinafter, inductor region 232/238_R, [0040] and [0041], Fig. 2), the semiconductor device structure further comprises an inductive element (Male, semiconductor device structure 548 further comprises an embedded inductor coil 510/510a which is an inductive element, hereinafter, inductive element 510/510a, [0044], Fig. 5; Piedra, first additional metallic device 232 and second additional metallic device 238 within inductor region 232/238_R may include an inductor, hereinafter, inductive element 232/238, [0040] and [0041], Fig. 2), the inductive element is positioned above the inductive region (Male, inductive element 510/510a is positioned above the inductive region, [0044], Fig. 5; Piedra, inductive element 232/238 is positioned above the inductive region 232/238_R, [0040] and [0041], Fig. 2), and the inductive region comprises at least one second trench arranged in a horizontal direction and extended in a vertical direction (Male, inductive region 510/510a comprises at least one second trench 522a, Fig. 5; Piedra, inductive region 232/238_R, [0040] and [0041], Fig. 2).
Claim 16, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 15.
Piedra/Male discloses wherein a projection shape of the second trench in the inductive region on a plane where the substrate is located is a star (Male, a projection shape of the at least one second trench 321/522a in the inductive region (i.e. overlapping the inductor 311) on a plane where the substrate 308 is located is a star, [0034], Figs. 3E and 5; Piedra, at least one second trench 208, [0036] and [0089], Figs. 2 and 6).
Claim 17, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 15.
Piedra/Male discloses wherein a density of the second trench in the inductive region decreases gradually from a center of the inductive region to an edge of the inductive region (Male, each second trench 321/522a is arranged in a star pattern having a density decrease gradually from the center of the inductive region to an edge of the inductive region, [0034], Figs. 3E and 5; Piedra, at least one second trench 208, [0036] and [0089], Figs. 2 and 6).
Claim 18, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 15.
Piedra/Male discloses wherein the inductive element comprises an inductive coil, and an area surrounded by the second trench at an outermost circle of the inductive region is greater than an area surrounded by an outermost contour of the inductive coil (Male, inductive element 311/321 comprises an inductive coil 311, and an area surrounded by the second trench 321 at an outermost circle of the inductive region is greater than an area surrounded by an outermost contour of the inductive coil 311, [0034], Figs. 3E and 5; Piedra, at least one second trench 208, [0036] and [0089], Figs. 2 and 6).
Claim 19, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 15.
Piedra/Male discloses wherein the inductive region of the substrate is adjacent to the transistor region (Male, inductive region 510/510a of the substrate 508/508a is adjacent to the transistor region, [0044], Fig. 5; Piedra, inductor region 232/238_R of the substrate 202 is adjacent to the transistor region 210/214/218, [0040] and [0041], Fig. 2).
Claim 20, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein the transistor comprises a barrier layer (Piedra, barrier layer 206/406/606¸ [0034], [0066], and [0085], Figs. 2, 4, and 6; Male, integrated semiconductor device structure 548, [0044], Fig. 5), a first dielectric layer (Piedra, second dielectric material layer 236 is a first dielectric layer, hereinafter, first dielectric layer 236, [0040], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) and a second dielectric layer (Piedra, first dielectric material 224 is a second dielectric layer, hereinafter, second dielectric layer 224, [0040], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) that are stacked sequentially (Piedra, first dielectric layer 236 and second dielectric layer 224 are stacked sequentially, [0040], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5);
a source, a gate and a drain that are located on the barrier layer (Piedra, source 212, a gate 208/630 and a drain 216 are located on the barrier layer 206/406/606, [0037], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5); and
a gate field plate structure (Piedra, first plate 220 has a gate field plate structure, hereinafter, gate field plate structure 220, [0038], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) penetrating through the second dielectric layer (Piedra, gate field plate structure 220 penetrates through the second dielectric layer 224, [0038], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Piedra in view of Male, further in view of Obata (US 2022/0310582 A1).
Claim 11, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male does not explicitly disclose wherein a depth of the first trench ranges from 15 μm to 80 μm and/or a depth of the second trench ranges from 15 μm to 80 μm.
However, Obata discloses wherein a depth of the first trench ranges from 15 μm to 80 μm and/or a depth of the second trench ranges from 15 μm to 80 μm (Obata, a depth of the first and/or second trench TR ranges from 15 μm to 80 μm (i.e. 15 μm to 80 μm), [0027], Fig. 2; Male, at least one first trench 522 and at least one second trench 522a are arranged in a horizontal direction and extend in a vertical direction, [0046], Fig. 5; Piedra, at least one first trench 242 and at least one second trench 208 are arranged in a horizontal direction and extend in a vertical direction, [0036] and [0042], Figs. 2, 4, and 6). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of trench depth (result effective at least insofar as trench depth may achieve a larger electric capacitance while also preventing damage (Obata, [0028])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed trench depth or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 12, Piedra/Male discloses the monolithically integrated semiconductor device structure (Piedra, monolithically integrated semiconductor device structure 200, [0033], Fig. 2; Male, integrated semiconductor device structure 548, [0044], Fig. 5) according to claim 1.
Piedra/Male discloses wherein a width of the first trench ranges from 0.5 μm to 5 μm, and/or a width of the second trench ranges from 0.5 μm to 5 μm (Obata, a width of the trench TR may be 5 μm, [0025], Fig. 2; Male, at least one first trench 522 and at least one second trench 522a are arranged in a horizontal direction and extend in a vertical direction, [0046], Fig. 5; Piedra, at least one first trench 242 and at least one second trench 208 are arranged in a horizontal direction and extend in a vertical direction, [0036] and [0042], Figs. 2, 4, and 6), and
the width of the first trench is greater than the width of the second trench (Male, the width of the at least one first trench 522 is greater than the width of the at least one second trench 522a, [0033], Fig. 5; Piedra, at least one first trench 242 and at least one second trench 208 are arranged in a horizontal direction and extend in a vertical direction, [0036] and [0042], Figs. 2, 4, and 6). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of trench width (result effective at least insofar as trench width may achieve a larger electric capacitance while also preventing damage (Obata, [0028])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed trench width or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kobayashi (US 2022/0415832 A1) discloses a monolithically integrated semiconductor device structure (tunable inductor device 34 includes a substrate 36 further comprising a monolithic microwave integrated circuit, hereinafter, monolithically integrated semiconductor device structure 34, [0035], Figs. 2 and 3), comprising: a substrate (substrate 14/36, [0034] and [0035], Figs. 2 and 3) comprising a transistor region (each patch of phase change material (PCM) 12 functions as a phase change switch (PCS) 40/46/52 and may be equated to a transistor region, hereinafter, transistor region 12, [0037]-[0039], Figs. 2 and 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights