DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: a typo is present in the phrase “each first upper lead of the first conductive patterns” in line 14, which is being interpreted to read “the first upper lead of the first conductive patterns” given the context of surrounding claim language. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0211972 A1 to Min et al. (hereinafter “Min”).
Regarding claim 1, Min discloses a chip-on-film (COF) package, comprising:
a base film having a first surface and a second surface, the second surface facing the first surface (COF semiconductor package 100 having film substrate 110 with first and second opposing surfaces; Fig. 3; paragraph [0042]);
at least one first upper pattern on the first surface of the base film and extending in a first direction (first set of wires extending between chips 310, 320 and BR1 region on first surface of substrate 110 and extending in Y direction; Fig. 7; paragraph [0085]);
a plurality of second upper patterns on the first surface of the base film, the plurality of second upper patterns including inner patterns and outer patterns that are spaced apart from each other in the first direction (second set of wires extending between chips 310, 320 and BR2 region and having first group of wires closer to chips 310, 320 and second group of wires closer to BR2 region, where first and second groups of wires are spaced apart in the Y direction; Fig. 7);
an upper insulating layer covering the at least one first upper pattern and part of the second upper patterns (epoxy resin mold film 130 covering at least one of first wires and part of second wires; Fig. 7; paragraph [0071]);
a plurality of lower patterns on the second surface of the base film and electrically connecting the inner patterns to the outer patterns (third set of wires on second side of substrate 110 which connect first and second groups of wires; Fig. 8); and
inner via plugs passing through the base film and electrically connecting the inner patterns of the second upper patterns to the plurality of lower patterns (vias filled with conductive material connecting first group of wires with third set of wires; Fig. 7; paragraphs [0089]-[0094]), wherein at least one of the inner patterns is electrically connected to the inner via plug in a region that is not covered by the upper insulating layer (at least one of first group of wires is connected to conductive vias in a region not covered by film 130; Figs. 7-11).
Regarding claim 2, Min discloses the COF package as claimed in claim 1, wherein: the inner patterns include first inner patterns and second inner patterns, and a length of each first inner pattern in the first direction is different from a length of each second inner pattern in the first direction (first group of wires includes first sub-group and second sub-group of wires having different lengths in the Y direction; Fig. 7).
Regarding claim 3, Min discloses the COF package as claimed in claim 2, wherein: the length of each first inner pattern in the first direction is less than the length of each second inner pattern in the first direction, and each first inner pattern contacts the inner via plug in the region that is not covered by the upper insulating layer (first sub-group of wires has smaller length in Y direction relative second sub-group of wires, where first sub-group of wires contacts the conductive vias in a region not covered by film 130; Figs. 7-11).
Regarding claim 4, Min discloses the COF package as claimed in claim 3, wherein: the at least one first upper pattern includes a first region and a second region, the first region is a region in which the first inner patterns are at opposite sides of the at least one first upper pattern, the second region is a region in which the first inner patterns are not at at least one of the opposite sides of the at least one first upper pattern (first set of wires includes a first region at the edges thereof including some of first group of wires and a second region not at the edges not including some of first group of wires; Fig. 7), and a length of the second region in a second direction that is perpendicular to the first direction is smaller than a length of the first region in the second direction (first set of wires in first region have a length in the X direction larger than that of the second region; Fig. 7).
Regarding claim 5, Min discloses the COF package as claimed in claim 3, wherein: the plurality of lower patterns include a first lower pattern and a second lower pattern, the first lower pattern is electrically connected to the first inner pattern, the second lower pattern is electrically connected to the second inner pattern (third set of wires includes first portion electrically connected to first group of wires and second portion electrically connected to second group of wires; Figs. 7-8), and a length of the first lower pattern in the first direction is greater than a length of the second lower pattern in the first direction (first portion of wires has greater length in Y direction than second portion of wires; Figs. 7-8).
Regarding claim 6, Min discloses the COF package as claimed in claim 5, wherein the first lower pattern has a bent shape (first portion of wires has bent shape; Figs. 7-8).
Regarding claim 7, Min discloses the COF package as claimed in claim 1, wherein the at least one first upper pattern and the inner patterns of the second upper patterns are spaced apart from each other in a second direction that is perpendicular to the first direction (first set of wires and second group of wires are spaced apart from each other in X-direction; Figs. 7-8).
Regarding claim 8, Min discloses the COF package as claimed in claim 7, wherein a length of the at least one first upper pattern in the first direction is greater than a length of each inner pattern of the second upper patterns in the first direction (length of first set of wires in Y direction is greater than that of second group of wires; Fig. 7).
Regarding claim 9, Min discloses the COF package as claimed in claim 7, wherein the at least one first upper pattern includes a plurality of regions having different lengths in the second direction (first set of wires in first region have a length in the X direction different than that of the second region; Fig. 7).
Regarding claim 10, Min discloses the COF package as claimed in claim 1, wherein: the at least one first upper pattern includes a plurality of first upper patterns, and the plurality of first upper patterns have different lengths in a second direction perpendicular to the first direction (first set of wires have varying length in the X direction; Fig. 7).
Regarding claim 11, Min discloses a chip-on-film (COF) package, comprising:
a base film having a first surface and a second surface facing the first surface (COF semiconductor package 100 having film substrate 110 with first and second opposing surfaces; Fig. 3; paragraph [0042]);
a plurality of first conductive patterns including: a first upper lead on the first surface of the base film (first plurality of wires including a first upper wire on first surface of substrate 110; Fig. 7; paragraph [0085]), a first lower lead on the second surface of the base film (first lower wire on second side of substrate 110; Fig. 8), and a first via plug electrically connecting the first upper lead to the first lower lead (first via filled with conductive material connecting first upper wire to first lower wire; Figs. 7-8; paragraphs [0089]-[0094]); and
a plurality of second conductive patterns including: a second upper lead on the first surface of the base film (second plurality of wires including a second upper wire on first surface of substrate 110; Fig. 7; paragraph [0085]), a second lower lead on the second surface of the base film (second lower wire on second side of substrate 110; Fig. 8), and a second via plug electrically connecting the second upper lead to the second lower lead (second via filled with conductive material connecting second upper wire to second lower wire; Figs. 7-8; paragraphs [0089]-[0094]), wherein: each first upper lead of the first conductive patterns extends in a first direction, the first upper lead in at least one first conductive pattern of the plurality of first conductive patterns extends straight in the first direction (first upper wire extends straight in Y direction; Fig. 7), and the first lower lead and the second lower lead are spaced apart from each other in the first direction (first lower wire spaced apart form second lower wire in Y direction; Fig. 8).
Regarding claim 12, Min discloses the COF package as claimed in claim 11, wherein, from among the plurality of first conductive patterns, the first lower lead in the plurality of first conductive patterns, of which the first upper lead straightly extends in the first direction, is bent (first lower wire is bent; Fig. 8).
Regarding claim 13, Min discloses the COF package as claimed in claim 11, further comprising an upper insulating layer covering at least part of the first upper lead of the plurality of first conductive patterns and at least part of the second upper lead of the plurality of second conductive patterns (epoxy resin mold film 130 covering at least part of first upper wire and at least part of second upper wire; Fig. 7; paragraph [0071]).
Regarding claim 14, Min discloses the COF package as claimed in claim 13, wherein, from among the plurality of first conductive patterns, the first via plug in the plurality of first conductive patterns, of which the first upper lead straightly extends in the first direction, is in a region that is not covered by the upper insulating layer (first conductive via in a region not covered by film 130; Figs. 7-11).
Regarding claim 15, Min discloses the COF package as claimed in claim 11, wherein the first upper lead of some of the plurality of first conductive patterns has a bent shape (first upper wire is bent; Fig. 7).
Regarding claim 16, Min discloses the COF package as claimed in claim 11, wherein: the plurality of first conductive patterns include a first group and a second group, the first group includes the first conductive patterns in which the first upper lead extends straight in the first direction, the second group includes the first conductive patterns in which the first upper lead extends in the first direction while being bent, and an extending length of the first upper lead in the first group is less than an extending length of the first upper lead in the second group (first group of wires includes first upper wire extending straight in Y direction and second group of wires includes first upper wire extending bent in Y direction, where part of straight portion has smaller length than bent portion; Fig. 7).
Regarding claim 17, Min discloses the COF package as claimed in claim 11, further comprising a semiconductor chip electrically connected to the first upper lead of the plurality of first conductive patterns and the second upper lead of the plurality of second conductive patterns (chip 310 electrically connected to first upper wire and second upper wire; Figs. 2 and 7), wherein, from among the plurality of first conductive patterns, the first via plug of the plurality of first conductive patterns, of which the first upper lead straightly extends in the first direction, is perpendicularly under the semiconductor chip (first conductive via extends in a perpendicular direction to plane of chip 310; Figs. 2 and 7-8).
Regarding claim 18, Min discloses a chip-on-film (COF) package, comprising:
a base film having a first surface and a second surface facing the first surface (COF semiconductor package 100 having film substrate 110 with first and second opposing surfaces; Fig. 3; paragraph [0042]);
at least one first upper pattern on the first surface of the base film and extending in a first direction (first set of wires extending between chips 310, 320 and BR1 region on first surface of substrate 110 and extending in Y direction; Fig. 7; paragraph [0085]);
a plurality of second upper patterns extending on the first surface of the base film in the first direction, and including inner patterns and outer patterns spaced apart from each other in the first direction (second set of wires extending between chips 310, 320 and BR2 region in Y direction and having first group of wires closer to chips 310, 320 and second group of wires closer to BR2 region, where first and second groups of wires are spaced apart in the Y direction; Fig. 7); and
a plurality of lower patterns on the second surface of the base film and electrically connecting the inner patterns to the outer patterns (third set of wires on second side of substrate 110 which connect first and second groups of wires; Fig. 8), wherein: the second upper patterns include a first group and a second group, and an extending length of the inner patterns of the first group in the first direction is different from an extending length of the inner patterns of the second group (first group of wires includes first sub-group and second sub-group of wires having different lengths in the Y direction; Fig. 7).
Regarding claim 19, Min discloses the COF package as claimed in claim 18, wherein an extending length in the first direction of the inner patterns of the first group is less than an extending length in the first direction of the inner patterns of the second group (first sub-group of wires has smaller length in Y direction relative second sub-group of wires; Figs. 7-11).
Regarding claim 20, Min discloses the COF package as claimed in claim 19, further comprising: an inner via plug passing through the base film and electrically connecting the inner patterns of the second upper patterns to the plurality of lower patterns (inner via filled with conductive material connecting first group of wires with third set of wires; Fig. 7; paragraphs [0089]-[0094]); and an outer via plug passing through the base film and electrically connecting the outer patterns of the second upper patterns to the plurality of lower patterns (outer via filled with conductive material connecting second group of wires with third set of wires; Fig. 7; paragraphs [0089]-[0094]), wherein the inner via plug connected to the second upper pattern of the first group is closer to the outer via plug than the inner via plug connected to the second upper pattern of the second group is to the outer via plug (inner conductive via connected to first group of wires is closer to outer conductive via than inner conductive via connected to second group of wires; Figs. 7-8).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0165671 A1 to Ikura and US 2017/0125314 A1 to Lim et al. each discloses COF packages having similar routing designs to the presently claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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