Prosecution Insights
Last updated: August 06, 2026
Application No. 18/607,921

GRAPHENE-BASED FET SENSOR ARRAY

Non-Final OA §102
Filed
Mar 18, 2024
Examiner
IQBAL, HAMNA FATHIMA
Art Unit
4100
Tech Center
4100
Assignee
Iplexmed Lda
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+22.4% vs TC avg
Strong +21% interview lift
Without
With
+21.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
44 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
61.9%
+21.9% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
14.9%
-25.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/12/2025 is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aran et al. (US 20220365024 A1). Regarding Claim 1, Aran et al. discloses a system, the system comprising: a silicon substrate 129 covered in an insulating layer 119 (not shown in Fig. 4 but shown in Fig. 7: 119, 129, paragraph 0179), configured with: an array 403 of sensors 406 (Fig. 4: 403, 406, paragraph 0167); a plurality of drain terminals 402 (Fig. 4: 402, paragraph 0169); and a source terminal 412 (Fig. 4: 412, paragraph 0170), wherein: each drain terminal 402 of the plurality of drain terminals 402 is configured to be electrically connected to a sensor 406 of the array 403 of sensors 406 (Fig. 4: 402, 406, 403, paragraph 0169), the source terminal 412 is configured to be electrically connected, via a common line, to each sensor 406 of the array 403 of sensors 406 (Fig. 4: 412, 403, 406, paragraph 0170), and the common line traverses the array of sensors in a serpentine pattern (Fig. 4: 412, paragraph 0170). Regarding Claim 2, Aran et al. discloses the system of claim 1, wherein the array 403 of sensors 406 comprises graphene sensors (paragraph 0063). Regarding Claim 3, Aran et al. discloses the system of claim 1, wherein a sensor 406 of the array 403 of sensors 406 is configured to form a channel between the source terminal 412 and one drain terminal 402 of the plurality of drain terminals 402 (Fig. 4: 412, 402, paragraph 0147, 0167). Regarding Claim 4, Aran et al. discloses the system of claim 1, wherein a conductivity of a sensor of the array of sensors is determined when an electric field applied at a gate terminal 407 (paragraph 0132, 0170, 0250). Note that paragraphs 0170 and 0250 states a voltage is applied to the gate electrode. Regarding Claim 5, Aran et al. discloses the system of claim 1, wherein a conductivity of a sensor of the array of sensors is determined according to a biological sample 120 applied to the sensor (see Fig. 7: 120, paragraph 0120). Regarding Claim 6, Aran et al. discloses the system of claim 1, wherein the system comprises a gate layer 108 on a plane above the silicon substrate 129 (Fig. 7: 108, 129, paragraph 0179, 0180). Note that the reference gate electrode 127 is formed in the metallization layer 108 and hence layer 108 is interpreted as the gate layer. Regarding Claim 7, Aran et al. discloses the system of claim 6, wherein the gate layer 108 and a sensor, of the array of sensors, are configured to be electrically connected via a biological sample applied to the sensor (paragraph 0063, 0132). Note that according to paragraphs 0063, the FETs are liquid-gated, meaning that current through the channel is modulated by interaction of ions, molecules, or moieties within the biological sample in the form of a liquid. Thus, the gate layer and the sensor in the channel are electrically coupled through the biological sample via ionic/electrolytic coupling. Regarding Claim 8, Aran et al. discloses the system of claim 6, wherein the gate layer 108 is configured to be electrically connected to a terminal 127 on the silicon substrate 129 (Fig. 7: 108, 127, 129, paragraph 0180). Regarding Claim 9, Aran et al. discloses the system of claim 6, wherein the gate layer 108 comprises a plurality of windows 136 that allow a biological sample 120 to be added to a sensor 106 of the array 103 of sensors 106 (Fig. 7: 136, 108, paragraph 0185). Note that Fig. 4 does not explicitly show the windows but mentions it in paragraph 0171 as liquid wells 402 (see Fig. 4: 402, paragraph 0171). Fig. 7 reading on a different embodiment shows the windows 136 explicitly in a cross-sectional view and thus is relied upon to teach the above limitations. Regarding Claim 10, Aran et al. discloses the system of claim 6, wherein: system comprise a cap 134 that covers the array 103 of sensors 106, and the gate layer 108 is applied to the cap 134 (Fig. 7: 134, paragraph 0133, 0185). Regarding Claim 11, Aran et al. discloses a method, the method comprising: adding a biological sample 120 onto each sensor 406 in an array 403 of sensors 406 on a silicon substrate 129 (Fig. 4: 129, 120, Fig. 4: 403, 406, paragraph 0152, 0167, 0179) ; Note that the silicon substrate and the biological sample is not explicitly shown in Fig. 4 but shown in Fig. 7 reading on a different embodiment. applying a first electrical signal to a common source terminal 412 on the silicon substrate (paragraph 0250), wherein the common source terminal 412 is electrically connected, via a common line in a serpentine pattern, to each sensor 406 of the array 403 of sensors 406 (Fig. 4: 412, 403, 406, paragraph 0170); applying a second electrical signal to a common gate terminal 407 on the silicon substrate, and determining a conductivity of a sensor 406 in the array 403 of sensors 406 at a corresponding drain terminal 402 of a plurality of drain terminals 402 (Fig. 4: 407, 402, 403, 406, paragraph 0169, 0170, 0250). Regarding Claim 12, Aran et al. discloses the method of claim 11, wherein the array 403 of sensors 406 comprises graphene sensors (paragraph 0063). Regarding Claim 13, Aran et al. discloses the method of claim 11, wherein a sensor 406 of the array 403 of sensors 406 is configured to form a channel between the common source terminal 412 and one drain terminal 402 of the plurality of drain terminals 402 (Fig. 4: 412, 402, paragraph 0147, 0167). Regarding Claim 14, Aran et al. discloses the method of claim 11, wherein the conductivities of two or more sensors in the array of sensors are determined in parallel (paragraph 0191). Note that paragraph 0191 states that the system allows for detection of multiple target analytes simultaneously. For example, one sensor is functionalized to detect a nucleic acid and another to detect a protein. Thus, the system will allow for the conductivities of these two sensors to be determined in parallel in order to detect multiple target analytes simultaneously. Regarding Claim 15, Aran et al. discloses the method of claim 11, wherein the conductivity of the sensor 406 of the array 403 of sensors 406 is determined according to a current measured at the corresponding drain terminal 402 (Fig. 4: 402, 403, 406, paragraph 0250, 0251). Regarding Claim 16, Aran et al. discloses the method of claim 11, wherein the gate terminal 127 is electrically connected to a gate layer 108 on a plane above the silicon substrate 129 (Fig. 7: 108, 127, 129, paragraph 0180). Note that the reference gate electrode 127 is formed in the metallization layer 108 and hence layer 108 is interpreted as the gate layer. Regarding Claim 17, Aran et al. discloses the method of claim 16, wherein the gate layer 108 and a sensor, of the array of sensors, are configured to be electrically connected via a biological sample applied to the sensor (paragraph 0063, 0132). Note that according to paragraphs 0063, the FETs are liquid-gated, meaning that current through the channel is modulated by interaction of ions, molecules, or moieties within the biological sample in the form of a liquid. Thus, the gate layer and the sensor in the channel are electrically coupled through the biological sample via ionic/electrolytic coupling. Regarding Claim 18, Aran et al. discloses the method of claim 16, wherein the method comprise covering the silicon substrate 129 with the gate layer 108 (Fig. 7: 129, 108, paragraph 0179). Regarding Claim 19, Aran et al. discloses the method of claim 16, wherein the biological sample 120 is added onto each sensor 106 of the array 103 of sensors 106 via a plurality of windows 136 in the gate layer 108 (Fig. 7: 136, 108, paragraph 0185). Note that Fig. 4 does not explicitly show the windows but mentions it in paragraph 0171 as liquid wells 402 (see Fig. 4: 402, paragraph 0171). Fig. 7 reading on a different embodiment shows the windows 136 explicitly in a cross-sectional view and thus is relied upon to teach the above limitations. Regarding Claim 20, Aran et al. discloses the method of claim 16, wherein the method comprises covering the silicon substrate with a cap 134 that covers the array of sensors (paragraph 0133, 0185). Conclusion The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang et al. (US 20240376529 A1) discloses a graphene-based FET bio-sensor Torriceli et al. (US 20230036979 A1) discloses a graphene-based FET bio-sensor Elias et al. (US 20220136996 A1) discloses a graphene-based FET bio-sensor Shimomura (US 20130095650 A1) discloses a FET with drain and source electrodes having a serpentine pattern Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 07/14/2026 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 18, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701987
SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE STRUCTURES
3y 6m to grant Granted Aug 04, 2026
Patent 12660673
Semiconductor Device and Method of Forming an Antenna-in-Package Structure
3y 2m to grant Granted Jun 16, 2026
Patent 12615900
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
4y 1m to grant Granted Apr 28, 2026
Patent 12593544
DISPLAY APPARATUS AND MANUFACTURING METHOD THEREFOR, AND MULTI-SCREEN DISPLAY APPARATUS USING SAME
3y 5m to grant Granted Mar 31, 2026
Patent 12581969
SEMICONDUCTOR DEVICE
3y 7m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+21.4%)
3y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 17 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month