Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2023-0039187 3/24/2023 and KR 10-2023-0064561 filed on 5/18/2023 The foreign application is not in English. The certified copies of the foreign priority applications have been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 10-2023-0039187 and KR 10-2023-0064561 that is not in English, an English translation of the non-English language foreign applications and a statement that the translations are accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign applications must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Objection 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 10-12, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (US Pub. 20110193224), hereinafter referred to as Ito.
Regarding claim 1, Ito teaches a semiconductor package comprising: a semiconductor chip (Ito, 1, Fig. 1A, para. 23, semiconductor elements in the substrate are not shown, per para. 23); a pad structure electrically (Ito 6, Fig. 1A, para. 27) connected to the semiconductor chip; a solder ball (Ito, 7, Fig. 1A, para 28) spaced apart from the semiconductor chip in a first direction (Note: First direction is vertical in Fig. 1A) and in contact with the pad structure; and an insulating layer (Ito, 5, Fig. 1A, para. 24, Ito states that 5 may be made up of silicon nitride, which para. 36 of the application describes as an inorganic insulating material) arranged between the semiconductor chip and the pad structure and in contact with the pad structure, wherein the insulating layer includes a first ring-shaped groove (Ito, 5b, Figs. 1A, 1B, para. 29) having a ring shape surrounding the pad structure, and the first ring-shaped groove is spaced apart from the pad structure (Ito, Figs. 1A, 1B).
Regarding claim 2, Ito teaches the semiconductor package of claim 1, wherein the first ring-shaped groove does not overlap the solder ball in the first direction (Ito, Fis. 1A, 1B).
Regarding claim 3, Ito teaches the semiconductor package of claim 1, wherein the pad structure comprises: an under bump metallization (UBM) pad (Ito, 6bm Fig. 1A, para. 27) having a ring shape; and a UBM via integrated with the UBM pad (Ito, 6b Fig. 1A, para. 27), wherein the UBM pad does not extend to the first ring-shaped groove (Ito, Fig. 1B, shows that insulation layer 5 is visible from above between the solder ball7 and the groove 5b.
Regarding claim 4, Ito teaches the semiconductor package of claim 3, wherein the pad structure further comprises a seed layer arranged between the UBM pad and the insulating layer or between the UBM via and the insulating layer (Ito, 6a, Fig. 1A, para. 27), wherein the seed layer comprises at least one of titanium (Ti), titanium dioxide (TiO2), chromium nitride (CrN), titanium carbon nitride (TiCN), and titanium aluminum nitride (TiAlN) (Ito, para. 27states 6a may be made of a titanium alloy).
Regarding claim 5, Ito teaches the semiconductor package of claim 1, wherein a depth of the first ring-shaped groove is less than a length of the pad structure in the first direction (Ito, Fig. 1A).
Regarding claim 7, Ito teaches the semiconductor package of claim 1, wherein the first ring-shaped groove has a uniform width in a circumferential direction with the pad structure (Ito, Figs 1A and 1B show the location of the pad structure 6, below bump 7) at a center of a ring shape of the ring-shaped groove 5b).
Regarding claim 10, Ito teaches the semiconductor package of claim 1, wherein a maximum diameter of the first ring-shaped groove (Ito, 5b, Fig. 6b) is greater than a diameter of the solder ball (Ito, 7, Fig. 5b).
Regarding claim 11, Ito teaches a semiconductor package comprising: a semiconductor chip (Ito, 1, Fig. 1A, para. 23, semiconductor elements in the substrate are not shown, per para. 23); a pad structure electrically (Ito 6, Fig. 1A, para. 27) providing a first surface (surface closest to layer 5) and a second surface (away from layer 5); an under bump metallization (UBM) pad (Ito, 6b, Fig. 1A, para. 27) disposed on the first surface and electrically connected to the semiconductor chip; a solder ball (Ito, 7, Fig. 1A, para. 28) spaced apart from the semiconductor chip in a first direction (NOTE: vertical) and in contact with the UBM pad; an insulating layer (Ito, 5, Fig. 1A, para. 24, Ito states that 5 may be made up of silicon nitride, which para. 36 of the application describes as an inorganic insulating material) arranged between the semiconductor chip and the UBM pad; and a seed layer (Ito, 6a, Fig. 1A, para. 27) conformally arranged between the UBM pad and the insulating layer, wherein a first groove (Ito, 5b, Figs. 1A, 1B, para. 29) having a ring shape that surrounds the UBM pad is provided in an upper surface of the insulating layer that is orthogonal to the first direction, the first groove and the UBM pad are spaced apart from each other, and the first groove does not overlap the solder ball in the first direction (Ito, Fig. 1B shows the groove 5b separated from solder ball 7 by an expanse of insulating later 5, because the solder ball is on top of the UBM pad 6, this demonstrates that the first groove is spaced apart from the UBM pad and does not overlap the solder ball in the first( vertical) direction).
Regarding claim 12, Ito teaches the semiconductor package of claim 11, wherein the UBM pad has a ring shape, (Ito Fig. 1B shows that the solder ball, 7 is circular, and Fig. 1A shows that the UBM pad 6 is conformal to the solder ball, therefore the pad has a ring shape), and a width of the UBM pad in a radial direction is greater than a maximum width of the first groove in the radial direction (Ito, Fig. 1A).
Regarding claim 19, Ito teaches a semiconductor package comprising: a semiconductor chip(Ito, 1, Fig. 1A, para. 23, semiconductor elements in the substrate are not shown, per para. 23) providing a first surface (surface closest to layer 5) and a second surface (away from layer 5); an under bump metallization (UBM) pad (Ito, 6b, Fig. 1A, para. 27) having a ring shape (Ito Fig. 1B shows that the solder ball, 7 is circular, and Fig. 1A shows that the UBM pad 6 is conformal to the solder ball, therefore the pad has a ring shape )and disposed on the first surface to be electrically connected to the semiconductor chip; a UBM via (Ito, 6b, Fig. 1A, para. 27) integrated with the UBM pad and extending towards the semiconductor chip; a solder ball ; a solder ball (Ito, 7, Fig. 1A, para. 28) spaced apart from the semiconductor chip in a first direction (first direction is vertical in Fig. 1A) and in contact with the UBM pad; and an insulating layer (Ito, 5, Fig. 1A, para. 24) arranged between the semiconductor chip and the UBM pad and comprising an opening (Ito, 5a, Fig. 1A, paras. 24-25)in which the UBM via is disposed, wherein a first groove (Ito, 5b, Figs. 1A, 1B, para. 29) having a ring shape is provided in an upper surface of the insulating layer that is orthogonal to the first direction, the first groove being spaced apart from the UBM pad by a fixed distance with the UBM pad at a center of the first groove, and the first groove does not overlap the solder ball in the first direction ((Ito, Fig. 1B shows the groove 5b separated from solder ball 7 by an expanse of insulating later 5, because the solder ball is on top of the UBM pad 6, this demonstrates that the first groove is spaced apart from the UBM pad and does not overlap the solder ball in the first( vertical) direction).
Claim Objection 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 1 above, and further in view of Shin (US Patent 6384464), hereinafter referred to as Shin.
Regarding claim 8, Ito teaches the semiconductor package of claim 1, but does not teach wherein the insulating layer comprises a second ring-shaped groove spaced apart from the first ring-shaped groove in a radial direction.
However Shin teaches a semiconductor device wherein around the pads (Shin 23, Fig. 6, Col. 4, lines 18-50) there are three grooves (Shin 29, 30, 31, Fig. 6, Col. 4, lines 18-50) in the dummy patterns (Shin, 25, 27, Col. 4, lines 18-50) of which the outer two (Shin 30, 31, Fig. 6) do not touch the pad and they are spaced apart and they may be circular (Shin, Col. 3, lines 50-63).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the structure of Ito with the second groove of Shin in order to maintain planarity during processing. (Shin Col. 4, lines 28-50).
Regarding claim 9, modified Ito teaches the semiconductor package of claim 8, wherein the second ring-shaped groove has a uniform width in a circumferential direction (Ito, Fig. 1B shows the first groove, 5b with a uniform width in a circumferential direction, Shin in Fig. 6 shows the spacing between linear portions of the grooves to remain constant, therefore in the example from Shin Clo. 3, lines 50-63 wherein the grooves are circular the width in a circumferential direction would remain constant.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 1 above, and further in view of Nakagawa (US 20070267757), hereinafter known as Nakagawa.
Regarding claim 6, Ito teaches the semiconductor package of claim 1, but does not teach wherein a width of the first ring-shaped groove in a radial direction decreases towards the semiconductor chip.
However, Nakagawa teaches a semiconductor device wherein a plurality of solder balls (Nakagawa, 30, Fig. 1(b), para. 27) are mounted on copper posts (Nakagawa 21, Fig. 1(b), para. 27). These solder balls are surrounded by a groove (Nakagawa, 23, Fig. 1(b), para. 28) in the resin layer (Nakagawa 20, Fig. 1(b), para. 26). Nakagawa also shows a variant of the groove with a tapered appearance (Nakagawa, 23” Fig. 6, para. 43) which may be adopted so that when the chip is bonded to another semiconductor device and an underfill material is used air is not easily caught in the groove (Nakagawa, para. 43).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the structure of Ito with the groove shape of Nakagawa to exclude air from the groove during underfill procedures (Nakagawa, para. 43).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 11 above, and further in view of Nakagawa.
Regarding claim 18, Ito teaches the semiconductor package of claim 11, but does not teach wherein a width of the first ring-shaped groove in a radial direction decreases towards the semiconductor chip.
However, Nakagawa teaches a semiconductor device wherein a plurality of solder balls (Nakagawa, 30, Fig. 1(b)) are mounted on copper posts (Nakagawa 21, Fig. 1(b)). These solder balls are surrounded by a trench (Nakagawa, 21, Fig. 1(b)) in the resin layer (Nakagawa 20, Fig. 1(b)). Nakagawa also shows a variant of the groove with a tapered appearance (Nakagawa, 23” Fig. 6) which may be adopted so that when the chip is bonded to another semiconductor device and an underfill material is used air is not easily caught in the groove (Nakagawa, 2007).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the structure of Ito with the groove shape of Nakagawa to exclude air from the groove during underfill procedures (Nakagawa, 2007).
Allowable Subject Matter
Claims 13-17 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, Ito teaches the semiconductor package of claim 11, but does not teach, nor does the prior art suggest wherein a second groove protruding from the first groove towards the UBM pad is provided in the upper surface of the insulating layer.
Regarding claims 14 and 15, they both depend from claim 13, and would thus be allowable if claim 13 was rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, Ito teaches the semiconductor package of claim 11, but does not teach, nor does the prior art suggest wherein a second groove protruding from the first groove in a radial direction away from the UBM pad is provided in the upper surface of the insulating layer.
Regarding claims 17, it depends from claim 13, and would thus be allowable if claim 13 was rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 20, Ito teaches the semiconductor package of claim 19, but does not teach, nor does the prior art suggest wherein a plurality of second grooves protruding from the first groove towards the UBM pad are provided in the upper surface of the insulating layer, and each of the plurality of second grooves are spaced apart from an adjacent second groove by a fixed circumferential distance in a circumferential direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kato (US 20140035139) teaches a pad structure encircled by a groove.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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