DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant's election with traverse of Group I and claims 1-7 and 14-20 in the reply filed on June 05, 2026 is acknowledged. The traversal is on the ground(s) that “Applicant respectfully submits that process claims 5-7 and respective product claims 1-3 are not distinct under MPEP 806.05(f).” This is found persuasive and claims 1-7 and 14-20 are under examination and claims 8-13 are withdrawn from further consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 15, the limitans “a second metal interconnect” is already recited in claim 14. It is not clear whether the limitation refers to the same “second metal interconnect” . Thus, the limitation renders the claim indefinite and clarification is required. As to claim 19, the limitation “the second die” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 14-20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2004/0238857 A1 to Beroz et al. (“Beroz”).
As to claim 1, Beroz discloses a die package, comprising: a routing substrate (1412, 1418) extending in a first direction, the routing substrate (1412, 1418) comprising a first metallization layer (1420, 1481, 1482) comprising a plurality of first metal interconnects (1420, 1482) and a plurality of second metal interconnects (1420, 1481); a die (1415) comprising a plurality of die interconnects (solder balls ¶ 0092) each extending in a second direction orthogonal to the first direction, each die interconnect (solder balls ¶ 0092) of the plurality of die interconnects (solder balls ¶ 0092) coupled to a first metal interconnect (1420, 1482) of the plurality of first metal interconnects (1420, 1482); and a plurality of entangled vertical interconnects (1426, 1428) coupled to a second metal interconnect (1420, 1481) of the plurality of second metal interconnects (1420, 1481), each of the plurality of entangled vertical interconnects (1426, 1428) disposed at an angle with respect to the second direction (See Fig. 19, ¶ 0003, ¶ 0091-¶ 0102) (Notes: the limitation “entangle” is defined as to catch or involve in or as if in a tangle; ensnare or enmesh by Dictionary.com). As to claim 2, Beroz discloses further comprising a mold layer (1436) disposed on the first metallization layer (1420, 1481, 1482); wherein each of the plurality of entangled vertical interconnects (1426, 1428) is at least partially disposed in the mold layer (1436) (See Fig. 19, ¶ 0098). As to claim 3, Beroz further discloses wherein the plurality of entangled vertical interconnects (1426, 1428) comprises a plurality of wire bonds (1426, 1428) (See ¶ 0095, ¶ 0096). As to claim 4, Beroz further discloses the die package of claim 1 integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (See ¶ 0003, ¶ 0101). As to claim 5, Beroz discloses a method of fabricating an integrated circuit (IC) package, comprising: fabricating a die package, comprising: providing a routing substrate (1412, 1418) extending in a first direction, the routing substrate (1412, 1418) comprising a first metallization layer (1420, 1481, 1482) comprising a plurality of first metal interconnects (1420, 1482) and a plurality of second metal interconnects (1420, 1481); coupling each of a plurality of die interconnects (solder balls ¶ 0092) of a die (1415) each extending in a second direction orthogonal to the first direction, to a first metal interconnect (1420, 1482) of the plurality of first metal interconnects (1420, 1482); and coupling each of a plurality of entangled vertical interconnects (1426, 1428) to a second metal interconnect (1420, 1481) of the plurality of second metal interconnects (1420, 1481), wherein each of the plurality of entangled vertical interconnects (1426, 1428) is disposed at an angle with respect to the second direction (See Fig. 19, ¶ 0091-¶ 0102) (Notes: the limitation “entangle” is defined as to catch or involve in or as if in a tangle; ensnare or enmesh by Dictionary.com). As to claim 6, Beroz discloses further comprising disposing a mold material (1436) on the first metallization layer (1420, 1481, 1482) at least partially encompassing each of the plurality of entangled vertical interconnects (1426, 1428) in a mold layer (1436) and the die (1415) (See Fig. 19, ¶ 0098). As to claim 7, Beroz further discloses wherein the plurality of entangled vertical interconnects (1426, 1428) comprises a plurality of entangled wire bonds (1426, 1428) (See ¶ 0095, ¶ 0096). As to claim 14, Beroz discloses an integrated circuit (IC) package, comprising: a first die package, comprising: a first routing substrate (1412, 1418) extending in a first direction, the first routing substrate (1412, 1418) comprising a first metallization layer (1420, 1481, 1482) comprising a plurality of first metal interconnects (1420, 1482) and a plurality of second metal interconnects 1420, 1481); a first die (1415) comprising a plurality of first die interconnects (solder balls ¶ 0092) each extending in a second direction orthogonal to the first direction, each first die interconnect (solder balls ¶ 0092) of the plurality of first die interconnects (solder balls ¶ 0092) coupled to a first metal interconnect (1420, 1482) of the plurality of first metal interconnects (1420, 1482); and a plurality of entangled vertical interconnects (1426, 1428) coupled to a second metal interconnect (1420, 1481) of the plurality of second metal interconnects (1420, 1481), each of the plurality of entangled vertical interconnects (1426, 1428) disposed at an angle with respect to the second direction; and an interposer substrate (1430) adjacent to the first die package in the second direction, the interposer substrate (1430) comprising: a second metallization layer (1438, 1429, 1434) comprising a plurality of third metal interconnects (1429) each coupled to an entangled vertical interconnect (1426, 1428) of the plurality of entangled vertical interconnects (1426, 1428) (See Fig. 19, ¶ 0091-¶ 0102) (Notes: the limitation “entangle” is defined as to catch or involve in or as if in a tangle; ensnare or enmesh by Dictionary.com). As to claim 15, Beroz further discloses wherein each of the plurality of entangled vertical interconnects (1426, 1428) is coupled to a second metal interconnect (1420, 1481) of the plurality of second metal interconnects (1420, 1481) unaligned in the second direction to a coupled third metal interconnect (1429) of the plurality of third metal interconnects (1429) (See Fig. 19). As to claim 16, Beroz further discloses wherein each second metal interconnect (1420, 1481) of the plurality of second metal interconnects (1420, 1481) does not intersect an axis in the second direction of a third metal interconnect (1429) of the plurality of third metal interconnects (1429) coupled together through an entangled vertical interconnect (1426, 1428) of the plurality of entangled vertical interconnects (1426, 1428) (See Fig. 19). As to claim 17, Beroz discloses further comprising a second electrical component (1490, 1400) comprising a plurality of second component metal interconnects (1431) each extending in the second direction, each second metal interconnect (1431) of the plurality of second component metal interconnects (1431) coupled to a third metal interconnect (1429) of the plurality of third metal interconnects (1429) (See Fig. 19, ¶ 0102). As to claim 18, Beroz further discloses wherein the second electrical component (1490, 1400) comprises a second IC package comprising: a second routing substrate (1412, 1418, 1430) extending in the first direction, the second routing substrate (1412, 1418, 1430) comprising a third metallization layer (1438, 1429, 1434) comprising a plurality of fourth metal interconnects (1429, 1434); and the plurality of second component metal interconnects (1431); wherein: each second metal interconnect (1431) of the plurality of second metal interconnects (1431) is coupled to a fourth metal interconnect (1429, 1434) of the plurality of fourth metal interconnects (1429, 1434); and each fourth metal interconnect (1429, 1434) of the plurality of fourth metal interconnects (1429, 1434) is further coupled to a third metal interconnect (1429) of the plurality of third metal interconnects (1429) (See Fig. 19, ¶ 0102). As to claim 19, Beroz further discloses wherein the interposer substrate (1430) further comprises a third metallization layer (1438, 1434) adjacent to the second die in the second direction, the third metallization layer (1438, 1434) comprises a plurality of fourth metal interconnects (1434) each coupled to a third metal interconnect (1429) of the plurality of third metal interconnects (1429) and a second component metal interconnect (1431) of the plurality of second component metal interconnects (1431) (See Fig. 19). As to claim 20, Beroz further discloses wherein the first die package further comprises a mold layer (1436) disposed on the first metallization layer (1420, 1481, 1482); wherein each of the plurality of entangled vertical interconnects (1426, 1428) is at least partially disposed in the mold layer (1436) (See Fig. 19, ¶ 0098).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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