DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-9 are amended. Claims 1-17 are present for examination.
Response to Arguments
Applicant's arguments filed July 27, 2026 in regard to the 35 U.S.C. 102 rejection of claim 10 have been fully considered but they are not persuasive.
As seen in Figs. 1D and 3B(d), the semiconductor base layer 150d may have a patterned surface (Lin, bonding material (i.e., the first bonding layer 150d) may also be a patterned bonding layer), [0039], Figs. 1D and 3B(d)) and serve as a base layer (Lin, semiconductor base layer 150d is patterned and serves as a patterned bonding layer (i.e. base layer), [0039], Figs. 1D and 3B(d)) and a filling structure 170 is disposed on the patterned surface to form a flat surface (Lin, filling structure 170 and flat patterned surface 150d are disposed on each other to form a flat surface (i.e. bonding material with a planar structure is firstly formed to cover on the micro epitaxial structures 120 via a film coating method, and is then formed into the patterned bonding layer through an etching process), [0039], Figs. 1D and 3B(d)).
Applicant’s arguments, see pages 6-8, filed July 27, 2026, with respect to the rejection(s) of claim(s) 1-9 under 35 U.S.C. 102 and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chiu (US 2016/0204305 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the following claim language;
the set order in which the plurality of semiconductor structures are formed (e.g. wherein the plurality of semiconductor structures are formed by performing the method of forming a plurality of semiconductor structures in sequential/chronological order)
the relative positioning of the filling structure with respect to the patterned surface of the semiconductor base (e.g. a filling structure is disposed in direct contact with the patterned surface to form a flat surface, wherein the filling structure and the patterned surface overlap in a vertical direction throughout the entire width of each light-emitting structure)
The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 1 of claim 1, it appears as ”… a method of forming a plurality of semiconductor structure …” should instead read as “… a method of forming a plurality of semiconductor structures …”.
For purposes of examination, the Examiner will interpret the limitation as “… a method of forming a plurality of semiconductor structures …”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2018/0076365 A1).
Claim 10, Lin discloses a semiconductor structure (light emitting device 100a’/100a/100b/100c/100d/100e/100f/100g is a semiconductor structure, hereinafter, semiconductor structure 100, [0022], Figs. 1A-2C), comprising:
a carrier substrate (first substrate 110 is a carrier substrate, hereinafter, carrier substrate 110, [0022], Figs. 1A and 1D); and
a plurality of light-emitting structures (plurality of micro epitaxial structures 120, bonding pad 130a/130d, and second substrate 140d are a plurality of light-emitting structures, hereinafter, plurality of light-emitting structures 120/130, [0022], Figs. 1A and 1D) is provided on the carrier substrate 110 (plurality of light-emitting structures 120/130 are provided on the carrier substrate 110, [0022], Figs. 1A and 1D), wherein each of the plurality of light-emitting structures 120/130 comprises:
a semiconductor base layer (first bonding layer 150d is a semiconductor base layer, hereinafter, semiconductor base layer 150d, [0028], Fig. 1D) having a patterned surface (semiconductor base layer 150d has a patterned surface (i.e. top surface), [0028], Fig. 1D) and a surface opposite to the patterned surface (semiconductor base layer 150d has a surface opposite to the patterned surface (i.e. bottom surface), [0028], Fig. 1D);
a first type semiconductor layer (first type semiconductor layer 122, [0023], Fig. 1D) disposed on the surface (i.e. bottom surface of semiconductor base layer 150d) (first type semiconductor layer 122 is disposed on the bottom surface of semiconductor base layer 150d, [0023], Fig. 1D);
a light-emitting layer (active layer 124 is a light-emitting layer, hereinafter, light-emitting layer 124. [0023], Fig. 1D) disposed on the first type semiconductor layer 122 (light-emitting layer 124 is disposed on the first type semiconductor layer 122, [0023], Fig. 1D);
a second type semiconductor layer (second type semiconductor layer 126, [0023], Fig. 1D) disposed on the light-emitting layer 124 (second type semiconductor layer 126 is disposed on the light-emitting layer 124, [0023], Fig. 1D); and
a filling structure (insulating layers 170 are a filling structure, hereinafter, filling structure 170, [0034], Fig. 1D) is disposed on the patterned surface to form a flat surface (filling structure 170 is disposed on the patterned surface to form a flat surface, [0034], Fig. 1D).
Claim 12, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 10.
Lin discloses wherein each of the plurality of light-emitting structures 120/130 further comprises:
a first electrode (first bonding pads 132d is a first electrode, hereinafter, first electrode 132d, [0034], Fig. 1D) being electrically connected to the first type semiconductor layer 122 (first electrode 132d is electrically connected to the first type semiconductor layer 122, [0034], Fig. 1D); and
a second electrode (second bonding pads 134d is a second electrode, hereinafter, second electrode 134d, [0034], Fig. 1D) being electrically connected to the second type semiconductor layer 126 (second electrode 134d is electrically connected to the second type semiconductor layer 126, [0034], Fig. 1D).
Claim 13, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 12.
Lin discloses wherein the filling structure 170 is disposed between the semiconductor base layer 150d and the carrier substrate 110 (filling structure 170 is disposed between the semiconductor base layer 150d and the carrier substrate 110, [0034], Fig. 1D).
Claim 14, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 12.
Lin discloses wherein the first electrode 132d and the second electrode 134d are disposed between the semiconductor base layer 150d and the carrier substrate 110 (first electrode 132d and the second electrode 134d are disposed between the semiconductor base layer 150d and the carrier substrate 110, [0034], Fig. 1D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chiu (US 2016/0204305 A1).
Claim 1, Lin discloses a method of forming a plurality of semiconductor structures (light emitting device 100a’/100a/100b/100c/100d/100e/100f/100g is a semiconductor structure, hereinafter, semiconductor structure 100, [0022], Figs. 1A-2C), comprising:
providing a substrate (first substrate 110 is a carrier substrate, hereinafter, carrier substrate 110, [0022], Figs. 1A and 1D);
forming an epitaxial structure (micro epitaxial structure 120 is an epitaxial structure, hereinafter, epitaxial structure 120, [0028], Fig. 1D) with a patterned surface facing the substrate 110 (epitaxial structure 120 has a patterned surface on the substrate 110, [0028], Fig. 1D);
removing the substrate 110 to expose the patterned surface of the epitaxial structure 120 (removing the substrate 110 to expose the patterned surface of the epitaxial structure 120, [0043], Figs. 1D and 3D(b));
forming a filling structure (insulating layers 170 are a filling structure, hereinafter, filling structure 170, [0034], Fig. 1D) on the patterned surface to form a flat surface (filling structure 170 is disposed on the patterned surface to form a flat surface, [0034], Fig. 1D); and
performing a singulation process on the epitaxial structure 120 to form the plurality of semiconductor structures (a singulation process is performed on the epitaxial structure 120 to form the plurality of micro epitaxial structures 120, bonding pad 130a/130d, and second substrate 140d are a plurality of light-emitting structures, hereinafter, plurality of light-emitting structures 120/130, [0022], Figs. 1A and 1D).
Lin does not explicitly disclose forming an epitaxial structure with a patterned surface facing the substrate.
However, Chiu disclose forming an epitaxial structure (Chiu, semiconductor epitaxial stack 110/2110 is an epitaxial structure, hereinafter, epitaxial structure 110/2110, [0093], Figs. 1A-1H and 4B; Lin, micro epitaxial structure 120 is an epitaxial structure, hereinafter, epitaxial structure 120, [0028], Fig. 1D) with a patterned surface facing the substrate (Chiu, epitaxial structure 110/2110 has a patterned surface facing the substrate 20/220, [0093], Figs. 1F and 4B; Lin, epitaxial structure 120 has a patterned surface on the substrate 110, [0028], Fig. 1D). The combination to utilize an epitaxial stack that is patterned and facing the substrate would allow for the substrate to function as a temporary substrate and allow for the use of a suitable growth substrate for growing a high quality semiconductor epitaxial structure of the semiconductor light-emitting device (Chiu, [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an epitaxial stack that is patterned and facing the substrate would allow for the substrate to function as a temporary substrate and allow for the use of a suitable growth substrate for growing a high quality semiconductor epitaxial structure of the semiconductor light-emitting device (Chiu, [0003]).
Claim 2, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 1.
Lin/Chiu discloses further comprising forming a first temporary substrate (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, second bonding layer 140a is a first temporary substrate, hereinafter, first temporary substrate 140a, [0030], Fig. 2C) on the epitaxial structure after forming the epitaxial structure (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first temporary substrate 140a is formed on the epitaxial structure 120 after forming the epitaxial structure 120, [0030], Fig. 2C).
Claim 3, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 2.
Lin/Chiu discloses further comprising forming a first glue layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first bonding layer 150a is a first glue layer, hereinafter, first glue layer 150a, [0030], Fig. 2C) between the epitaxial structure and the first temporary substrate (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first glue layer 150a is formed between the epitaxial structure 120 and the first temporary substrate 140a, [0030], Fig. 2C).
Claim 4, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 2.
Lin/Chiu discloses, further comprising:
forming a second temporary substrate (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, second bonding layer 160 is a second temporary substrate, hereinafter, second temporary substrate 160, [0030], Figs. 1D and 3C(b)) on the flat surface (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, second temporary substrate 160 is on the flat surface, [0030], Figs. 1D and 3C(b)); and
removing the first temporary substrate after the flat surface is formed (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first temporary substrate 140a after the flat surface is formed, Fig. 1D).
Claim 6, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 1.
Lin/Chiu discloses wherein a laser lift-off process is performed for removing the substrate 110 (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, a laser lift-off process is performed for removing the substrate 110, [0043], Fig. 3D(b)).
Claim 7, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 1.
Lin/Chiu discloses wherein the epitaxial structure 120 includes:
a semiconductor base layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first bonding layer 150d is a semiconductor base layer, hereinafter, semiconductor base layer 150d, [0028], Fig. 1D) having the patterned surface (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor base layer 150d has a patterned surface (i.e. top surface), [0028], Fig. 1D);
a first type semiconductor layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first type semiconductor layer 122, [0023], Fig. 1D) is disposed on a surface opposite to the patterned surface (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, first type semiconductor layer 122 is disposed on the bottom surface of semiconductor base layer 150d (i.e. bottom surface of semiconductor base layer 150d), [0023], Fig. 1D);
a light-emitting layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, active layer 124 is a light-emitting layer, hereinafter, light-emitting layer 124. [0023], Fig. 1D) disposed on the first type semiconductor layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, light-emitting layer 124 is disposed on the first type semiconductor layer 122, [0023], Fig. 1D); and
a second type semiconductor layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, second type semiconductor layer 126, [0023], Fig. 1D) disposed on the light-emitting layer (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, second type semiconductor layer 126 is disposed on the light-emitting layer 124, [0023], Fig. 1D).
Claim 8, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 1.
Lin/Chiu discloses wherein forming the filling structure on the patterned surface is performed after forming the light-emitting structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, forming the filling structure 170 on the patterned surface is performed after forming the light-emitting structures 120/130, [0024], Figs. 1A-2C).
Claim 9, Lin/Chiu discloses the method of forming the plurality of semiconductor structures (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 2.
Lin/Chiu discloses wherein the substrate comprises a sapphire, SiC, or AlN (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, substrate 110 comprises sapphire, [0032], Fig. 1D).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chiu, and further in view of Benaissa (US 2021/0050476 A1).
Claim 5, Lin/Chiu discloses the method of forming the semiconductor structure (Chiu, semiconductor light-emitting device 300, [0116], Fig. 4B; Lin, semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 2.
Lin/Chiu does not explicitly disclose further comprising forming a second glue layer between the flat surface and the second temporary substrate.
However, Benaissa discloses further comprising forming a second glue layer (Benaissa, bonding layer 153 is a second glue layer, hereinafter, second glue layer 153¸ [0067], Fig. 6; Lin, glue layer 150a, [0030], Fig. 2C) between the flat surface and the second temporary substrate (Benaissa, second glue layer 153 is between the flat surface and the second temporary substrate 151¸ [0067], Fig. 6; Lin, glue layer 150a, [0030], Fig. 2C). The combination utilize a second glue layer allows for an improved alignment accuracy for resultant light-emitting devices (Benaissa, [0010).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a second glue layer to allow for an improved alignment accuracy for resultant light-emitting devices (Benaissa, [0010).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Benaissa.
Claim 16, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 10.
Lin does not explicitly disclose further comprising a glue layer disposed between the carrier substrate and the plurality of light-emitting structures.
However, Benaissa discloses further comprising a glue layer (Benaissa, polymer glue layer 153 is a glue layer, hereinafter, glue layer 153, [0075], Fig. 7; Lin, second bonding layer 160 is a glue layer, hereinafter, glue layer 160, [0033], Figs. 1A-2C) disposed between the carrier substrate and the plurality of light-emitting structures (Benaissa, glue layer 153 is disposed between the carrier substrate 151 and the plurality of light-emitting structures (i.e. active stack 120, [0074], Fig. 7), [0075], Fig. 7; Lin, glue layer 160 is disposed between the carrier substrate 110 and the plurality of light-emitting structures 120/130, Figs. 1A-2C). The combination to utilize a glue layer enables removal of the substrate by means of a chemical solution or by irradiation with an ultraviolet radiation (Benaissa, [0075]), resulting in a light-emitting device having improved alignment accuracy (Benaissa, [0010]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a glue layer to enable the removal of the substrate by means of a chemical solution or by irradiation with an ultraviolet radiation (Benaissa, [0075]), resulting in a light-emitting device having improved alignment accuracy (Benaissa, [0010]).
Claim 17, Lin/Benaissa discloses the semiconductor structure of claim 16.
Lin/Benaissa discloses wherein the glue layer comprises a thermal removable tape, a photoremovable adhesive film, a chemical removable tape, a heat-resistant tape, a blue film, or a tape with a dynamic release layer (Benaissa, glue layer 153 comprises a thermal removable tape, photoremovable adhesive film, chemical removable tape, etc., [0075], Fig. 7; Lin, glue layer 160, [0033], Figs. 1A-2C).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kischkat et al., “Mid-infrared optical properties of thin films of aluminum oxide, titanium dioxide, silicon dioxide, aluminum nitride, and silicon nitride”.
Claim 11, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 10.
Lin discloses wherein the filling structure 170 (i.e. silicon dioxide, alumina, silicon nitride, [0024]) comprises a material different from that of the semiconductor base layer 150d (i.e. film coating and spin coating methods may be used which are known in the art to include insulating materials such as silicon dioxide, alumina, silicon nitride).
Lin does not explicitly disclose wherein a refractive index difference between the filling structure and the semiconductor base layer is less than 0.5.
However, Lin/Kischkat discloses wherein a refractive index difference between the filling structure and the semiconductor base layer is less than 0.5 when either (I) the filling structure is formed of alumina and the semiconductor base layer is formed of silicon nitride (i.e. 2.011 – 1.76 = 0.251), (II) the filling structure is formed of silicon nitride and the semiconductor base layer is formed of alumina (i.e. 1.76 – 2.011 = -0.251), (III) the filling structure is formed of silicon dioxide and the semiconductor base layer is formed of alumina (i.e. 1.457 – 1.76 = -0.303), and (IV) the filling structure is formed of alumina and the semiconductor base layer is formed of silicon dioxide (i.e. 1.76 – 1.457 = 0.303).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of refractive index difference between adjacent filling structure and semiconductor base layer (result effective at least insofar as the refractive index difference between materials (i.e. silicon oxide, silicon nitride, and/or alumina) may form low-tolerance optical coatings within the optical spectrum without the use of expensive and potentially hazardous materials (Kischkat, Summary)) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed refractive index difference or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Ahmed (US 2018/0175248 A1).
Claim 15, Lin discloses a semiconductor structure (semiconductor structure 100, [0022], Figs. 1A-2C) according to claim 10.
Lin discloses wherein the carrier substrate 110 comprises sapphire (carrier substrate 110 is formed of sapphire, [0023]).
Lin does not explicitly disclose wherein the carrier substrate comprises silicon, and silicon carbide.
However, Ahmed discloses wherein the carrier substrate (Ahmed, carrier 305 is a carrier substrate, hereinafter, carrier substrate 305, [0033], Fig. 3I; Lin, carrier substrate 110, [0023], Fig. 1D) comprises silicon, sapphire, and silicon carbide (Ahmed, carrier substrate 305 comprises silicon, sapphire, and silicon carbide (i.e. SiC), [0033], Fig. 3I; Lin, carrier substrate 110, [0023], Fig. 1D. The combination to utilize silicon, sapphire, and/or silicon carbide as a carrier substrate enables suitable microstructure to improve lattice match with overgrowth material and/or promote polar or non-polar crystalline growth directions (Ahmed, [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize silicon, sapphire, and/or silicon carbide as a carrier substrate to enable suitable microstructure to improve lattice match with overgrowth material and/or promote polar or non-polar crystalline growth directions (Ahmed, [0033]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jang (US 2018/0151780 A1) discloses a light emitting device including the use of blue tape (i.e. blue film) as a glue layer.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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