Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive. In particular, with regards to rearranging the location of the third power supply line of Ishii et al to a second side of the substrate as disclosed by Takeno et al, it would be obvious per MPEP 2144.04 VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
C. Rearrangement of Parts
In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice). One of ordinary skill in the art can recognize that a power supply line delivers power, and locating a power supply line on a different side of the substrate with disclosed connection [from Takeno et al] would be obvious as it would not render the device completely inoperable. The third power line would still deliver power to the device. The specific location of the third power line is described by Takeno et al and no Ishii et al, thus arranging it according to how Takeno et al discloses would continue delivering power to the device (one of ordinary skill would not sever the other power lines as suggested by the Applicant), and as Takeno et al details in paragraph 0044, there is motivation to do so to reduce power consumption by using a power switch [which is the physical limitation described by Takeno et al]. Therefore, there is also not impermissible hindsight as there is a clear motivation for making this modification. Applicant argues Ishii has already achieved reduced power consumption through its unique front-side layout, but what is it reduced from, technological advances are always beneficial to further reduce the power consumption and give more function to the system at hand.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-8, and 10-11
are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al (JP 2015220250) in view of Takeno et al et al (US 20210210468).
Ishii et al teaches
[claim 1] A semiconductor device comprising: a substrate including a first surface and a second surface opposite to the first surface (figure 7, paragraph 0043, where element 61 is the substrate, where the first side of the substrate is the top side and the second side of the substrate is the bottom side);
a first power supply line provided on the first surface (figure 8, paragraphs 0054-0055, where element L5 in section 71 is the first power supply line and situated on the first surface of the substrate);
a second power supply line provided on the first surface (figure 8, paragraphs 0054-0055, where element L2 is the second power supply line and situated on the first surface);
a first ground line provided on the first surface (figure 8, paragraphs 0026, 0054-0055, element L3 is the first ground line on a first surface of the substrate, since element L3 is set at VSS [ground potential]);
a third power supply line (figure 8, paragraphs 0054-0055, where element L1 is the third power supply line);
a via provided on the substrate and electrically connecting the first power supply line and the third power supply line (figure 8, paragraph 0056, element TH2 connects element L5 in section 71 [first power supply line] and L1 [third power supply line]);
a fourth power supply line electrically connected to the second power supply line; (figure 8, paragraphs 0054-0055, element L6 in section 73 is the fourth power supply line and electrically connected to the second power supply line [element L2]);
a second ground line provided on the first surface (figure 8, paragraphs 0026, 0054-0055, where element L4 is the second ground line set at voltage VSS);
a first area including the second power supply line, the first ground line, the third power supply line, and the via (figure 8, paragraph 0054-0055, section 71 contains the first ground line [element L3], the first power supply line [element L5] and the third power supply line [element L1]);
a second area including the fourth power supply line and the second ground line (figure 8, paragraphs 0054-0055, where section 73 is the second area including a fourth power supply line [element L6 in section 73] and the second ground line [element L4]);
a third area positioned between the first area and the second area in plan view (figure 8, paragraphs 0054-0055, where section 72 is the third area situated between the first [section 71] and second [section 73] areas in plan view);
However, Ishii et al does not specifically disclose
[claim 1] a third power supply line provided on the second surface
and a power switch circuit including a switch transistor electrically connected between the first power supply line and the second power supply line.
However, Takeno et al does teach
[claim 1] a third power supply line provided on the second surface (figure 1, paragraph 0051, where element 11 is the substrate, and element 16 is the third power supply line. Read on from Ishii et al, elements 24 in section 20 contain the first, second and fourth power supply lines, as well as the first and second ground lines [five lines])
and a power switch circuit including a switch transistor electrically connected between the first power supply line and the second power supply line (abstract, where a power switch is connected between the first and second power supply lines [elements L5 of section 71 of Ishii et al and L2]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Ishii et al to incorporate the teachings of Takeno et al to reduce power consumption by instituting a power line and power switch [paragraph 0044].
Regarding claims
Ishii et al further teaches
[claim 6] The semiconductor device as claimed in claim 1, wherein the first power supply line and the second power supply line extend in a first direction, and are arranged apart from each other in the first direction in plan view (figure 8, paragraphs 0054-0055, where elements L5 and L2 in section 71 extend in a first direction [x-direction] and also are spaced apart in the x-direction).
[claim 8] The semiconductor device as claimed in claim 1, wherein the third power supply line is electrically connected to a plurality of first power supply lines in common (figure 8, paragraphs 0054-0055, where element L5 ins sections 71 and 73 are a plurality of first power supply lines, and are connected to the third supply power line [element L1]).
[claim 10] The semiconductor device as claimed in claim 1, wherein the second power supply line and the fourth power supply line extending in a first direction differ from each other in positions in a second direction different from the first direction, and wherein the second power supply line and the fourth power supply line are connected to each other through a first interconnect (figure 8, paragraphs 0054-0055, where element L6 in section 73 [fourth power supply line] extends in a first direction [it has a width in the x-direction], and the second power supply line [element L2] also extends in a first direction, and are spaced from each other in a second direction [y-direction] and are connected through an interconnect TH2).
[claim 11] The semiconductor device as claimed in claim 1, wherein the fourth power supply line is provided on the first surface (figure 8, paragraphs 0054-0055, where element L2 is on a first side of the substrate).
Regarding claims 2-4
Ishii et al as modified teaches all of the limitations of the parent claim, claim 1, as well as
[claim 3] The semiconductor device as claimed in claim 2, wherein the third area includes both a fifth power supply line electrically connected to the first power supply line and a sixth power supply line electrically connected to the second power supply line (figure 8, paragraphs 0054-0055, where section 72 is the third area, and elements L5 and L6 are the fifth and sixth power supply, where element L5 can be connected electrically to the first power supply line [element L5 of section 71] if set at the same voltage [see paragraphs 0026 and 0054-0055], similarly element L6 in section 72 [sixth power supply line] can be the same voltage as the second power supply line [element L2] and thus be electrically connected).
However, Ishii et al as modified does not specifically disclose
[claim 2] The semiconductor device as claimed in claim 1, wherein the power switch circuit is provided in the third area.
[claim 3] and wherein the switch transistor is electrically connected to the fifth power supply line and the sixth power supply line.
[claim 4] The semiconductor device as claimed in claim 1, wherein the power switch circuit is provided in the first area.
Taken et al further teaches
[claim 2] The semiconductor device as claimed in claim 1, wherein the power switch circuit is provided in the third area (abstract, when read onto Ishii et al, the switch is electrically between first and second power line of which the third section of Ishii et al [section 73] contains the second second power supply and one of the first plurality of first supply lines [element L5]).
[claim 3] and wherein the switch transistor is electrically connected to the fifth power supply line and the sixth power supply line (abstract, where if the first and second power supply line are electrically connected, and the fifth and sixth are connected to the first and second, the switch is electrically connected to the fifth and sixth power supply lines).
[claim 4] The semiconductor device as claimed in claim 1, wherein the power switch circuit is provided in the first area (abstract, when read onto Ishii et al, the switch is between first and second power line of which are in the first area [section 71]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Ishii et al to incorporate the teachings of Takeno et al to reduce power consumption by instituting a power switch [paragraph 0044].
Regarding claim 7,
Ishii et al as modified teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose
[claim 7] The semiconductor device as claimed in claim 6, wherein the first power supply line, the second power supply line, and the fourth power supply line are arranged apart from each other in the first direction in plan view.
However, according to MPEP 2144.04 VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
C. Rearrangement of Parts
In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Ishii et al to rearrange the direction of the first, second and fourth power lines to improve spatial efficiency of the device without changing any of the functional characteristics of the device.
Allowable Subject Matter
Claims 5 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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