DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (FIG. 3, Claims 1-20) in the reply filed on 7/16/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 3/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 10, 11-16 and 17-20 are objected to because of the following informalities:
Re Claim 10, line 3 references “the first portion”, which should be “a corresponding first portion of the plurality of first portions” to maintain consistent syntax and antecedent basis with “a plurality of first portions” in lines 10-11 of Claim 1.
Re Claim 11, line 6 references “the conductive lines”, which should be “the plurality of conductive lines” for consistency with line 3 of Claim 11.
Re Claim 17, line 14 references “the plurality of first portions”, when “a plurality of first portions” was not previously established. For the purposes of examination, “the plurality of first portions” will be interpreted as “the first portion”.
Re Claim 18, lines 1-2 reference “the plurality of first portions”, when “a plurality of first portions” was not previously established. For the purposes of examination, “the plurality of first portions” will be interpreted as “the first portion”.
Re Claim 19, lines 6-7 reference “a corresponding first conductive line of the plurality of conductive lines”, where it is unclear if these are the same set of conductive lines as the already claimed “corresponding conductive lines of the plurality of conductive lines” in lines 10-11 of Claim 17. For the purposes of examination, they will be assumed to be referring to the same set of conductive lines.
Claims 12-16 inherit the objection to Claim 11 due to their dependence from Claim 11. Claims 18-20 inherit the objection to Claim 17 due to their dependence from Claim 17.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Particularly, in line 4 of Claim 10, “a corresponding conductive contact of the second conductive contacts” is recited when “second conductive contacts” were not previously established. Thus, for Claim 20, “a corresponding conductive contact of the second conductive contacts” will be interpreted as just “a corresponding conductive contact”.
Additionally, in line 14 of Claim 17, “the plurality of first portions” has no attributable meaning because there is no clearly defined “plurality of first portions”, only “a first portion” was previously established in line 12 of Claim 17. Similarly, in line 2 of Claim 20, “a recess region, which is disposed between the first portions” has no attributable meaning because there is no clearly defined “first portions”. Thus, Claim 17 will be examined interpreting “the plurality of first portions” in line 14 as “the first portion”, and Claim 20 will be examined without considering the limitation “which is disposed between the first portions” in line 2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by a first interpretation of Lin et al (US 2022/0406994 A1, hereafter Lin).
Re Claim 1, Lin discloses a magnetic memory device (FIG. 6; [0020]-[0021]), comprising:
a plurality of conductive lines (12; [0012]) provided in a cell region (102; [0011]) and a peripheral region (104; [0012]);
a first insulating layer (10; [0011]) provided in the cell region (102; [0011]) and the peripheral region (104; [0011]), and surrounding the plurality of conductive lines (12; [0012]);
a second insulating layer (14, 26; [0014]) provided on the first insulating layer (10) in the cell region (102; [0014]) and the peripheral region (104; [0014]), and on top surfaces of the plurality of conductive lines (12; [0014]); and
a plurality of data storage patterns (106; [0011]) provided on the second insulating layer (14, 26) in the cell region (102; [0011]) and electrically connected to corresponding first conductive lines (12, in 102; [0011]) of the plurality of conductive lines (12; [0013]),
wherein the second insulating layer (14, 26) in the peripheral region (104) comprises a plurality of first portions (P1, see FIG. Z1 below) on the top surfaces of corresponding second conductive lines (12, in 104; [0011]) of the plurality of conductive lines (12; [0011]), and a plurality of second portions (P2, see FIG. Z1 below) disposed between the plurality of first portions (P1; [0011]), and
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top surfaces of the plurality of first portions (P1) are disposed at a level higher than top surfaces of the plurality of second portions (P2).
FIG. Z1: Annotated version of FIG. 6 of Lin
Re Claim 3, Lin discloses the magnetic memory device according to Claim 1, while further disclosing the device comprises a plurality of bottom electrode contacts (18; [0013]) provided between the plurality of data storage patterns (106) and the plurality of conductive lines (12; [0013]),
wherein the plurality of bottom electrode contacts (18) are connected to the plurality of data storage patterns (106), respectively ([0013]),
each of the plurality of bottom electrode contacts (18) is connected to a corresponding conductive line (12) of the first conductive lines (12, in 102; [0013]), and
a height of the plurality of bottom electrode contacts (18) is equal to a vertical thickness of the plurality of first portions (14, 26, combined; [0013]).
Re Claim 4, Lin discloses the magnetic memory device according to Claim 3, while further disclosing the device comprises a plurality of first cell conductive lines (34A; [0020]), which are disposed on the plurality of data storage patterns (106; [0020]) and are connected to the plurality of data storage patterns (106; [0020]).
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Re Claim 5, Lin discloses the magnetic memory device according to Claim 1, while further disclosing wherein the second insulating layer (14, 26) in the peripheral region (104) has a first recess region (R1, see FIG. Z2 below; [0011]), which is recessed toward the first insulating layer (10) between the plurality of first portions (P1; [0011], see FIG. Z2 below).
FIG. Z2: Annotated version of FIG. 6 of Lin
Re Claim 6, Lin discloses the magnetic memory device according to Claim 5, while further disclosing the device comprises a peripheral insulating layer (28; [0017]) provided on the second insulating layer (14, 26) in the peripheral region (104; [0017]), wherein the peripheral insulating layer (28) fills the first recess region (R1; [0017]), and the peripheral insulating layer (28) has a dielectric constant less than the second insulating layer ([0014]-[0017], silicon oxide in 28 lower than silicon nitride in 26).
Re Claim 7, Lin discloses the magnetic memory device according to Claim 1, while further disclosing wherein the plurality of first portions (P1) have different crystal structures from the plurality of second portions (P2; [0014], silicon nitride in 26 in P1 has different structure than silicon oxide in 14 in P2 due to the different material constituent characteristics of nitrogen and oxygen).
Re Claim 9, Lin discloses the magnetic memory device according to Claim 3, while further disclosing wherein the second insulating layer (14, 26) in the cell region (102) has a second recess region (R2, see FIG. Z2; [0011]), which is recessed toward the first insulating layer (10) between the plurality of data storage patterns (106; [0013]), and a lowermost portion of a top surface of the second recess region (R2) is located at a level lower than a top surface of the plurality of bottom electrode contacts (18; [0014]).
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by a second interpretation of Lin.
Re Claim 1, Lin discloses a magnetic memory device (FIG. 6; [0020]-[0021]), comprising:
a plurality of conductive lines (12; [0012]) provided in a cell region (102; [0011]) and a peripheral region (104; [0012]);
a first insulating layer (10; [0011]) provided in the cell region (102; [0011]) and the peripheral region (104; [0011]), and surrounding the plurality of conductive lines (12; [0012]);
a second insulating layer (14, 26; [0014]) provided on the first insulating layer (10) in the cell region (102; [0014]) and the peripheral region (104; [0014]), and on top surfaces of the plurality of conductive lines (12; [0014]); and
a plurality of data storage patterns (106; [0011]) provided on the second insulating layer (14, 26) in the cell region (102; [0011]) and electrically connected to corresponding first conductive lines (12, in 102; [0011]) of the plurality of conductive lines (12; [0013]),
wherein the second insulating layer (14, 26) in the peripheral region (104) comprises a plurality of first portions (26) on the top surfaces of corresponding second conductive lines (12, in 104; [0011]) of the plurality of conductive lines (12; [0011]), and a plurality of second portions (14) disposed between the plurality of first portions (26; [0011]), and
top surfaces of the plurality of first portions (26) are disposed at a level higher than top surfaces of the plurality of second portions (14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over the first interpretation of Lin, as applied to Claim 1, in view of Kao et al (US 2023/0138005 A1, hereafter Kao).
Re Claim 2, Lin discloses the magnetic memory device according to Claim 1, while further disclosing wherein a width of the plurality of first portions (P1) in the first direction (left to right in FIG. 6; [0011]) is greater than or equal to a width of the plurality of conductive lines (12) in the first direction (left to right in FIG. 6; [0012], equal).
Lin does not explicitly disclose wherein the device comprises a substrate provided in the cell region (102) and the peripheral region (104),
wherein the first insulating layer (10) is provided on the substrate,
the cell region (102) and the peripheral region (104) of the substrate extend in a first direction (left to right in FIG. 6) that is parallel to a top surface of the substrate.
However, Kao teaches a magnetic memory device (FIG. 10; [0054]) comprising wherein the device comprises a substrate (302, 320; [0054]) provided in the cell region (100A; [0013]) and the peripheral region (100B, 100C; [0013]),
wherein the first insulating layer (110; [0017]) is provided on the substrate (302, 320; [0054]),
the cell region (100A) and the peripheral region (100B, 100C) of the substrate (302, 320) extend in a first direction (left to right in FIG. 10) that is parallel to a top surface of the substrate (302, 320; [0054]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Claim 1 with the limitations taught by Kao to include a substrate (Kao: 302, 320) underlying the device to allow for inclusion of transistors connected to the overlying device for controlling storage as taught by Kao ([0054]-[0055]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the first interpretation of Lin, as applied to Claim 1, in view of Kuroda et al (US 6265822 B1, hereafter Kuroda).
Re Claim 8, Lin discloses the magnetic memory device according to Claim 1, but does not explicitly disclose wherein the second insulating layer (14, 26) comprises a carbon nitride (CN), and
a fraction of a sp3 C-N bonding in the plurality of first portions (P1) is greater than a fraction of a sp3 C-N bonding in the plurality of second portions (P2).
Kuroda discloses a device (column 9, lines 1-4) comprising wherein the second insulating layer (23; column 9, lines 1-4) comprises a carbon nitride (CN) (column 9, lines 1-4).
By specifying the nitride layer 26 of Lin is carbon nitride with sp3 C-N bonding, the plurality of first portions P1 of the second insulating layer (14, 26) in Lin, specifically the layer 26 of P1, has a fraction of sp3 C-N bonding greater than a fraction of sp3 C-N bonding in the silicon oxide layer 14 of the plurality of second portions P2 of the second insulating layer (14, 26) (as silicon oxide would have none).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Claim 1 with the limitations taught by Kuroda to specify the second insulating layer’s nitride layer (Lin: 26) is carbon nitride as a functionally equivalent material for a nitride layer providing insulation as taught by Kuroda (column 9, lines 1-4).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over the second interpretation of Lin, as applied to Claim 1, in view of Kao.
Re Claim 10, Lin discloses the magnetic memory device according to Claim 1, while further disclosing the device comprises a peripheral conductive line (34B; [0020]) provided on the first insulating layer (10) in the peripheral region (104; [0020]),
wherein the peripheral conductive line (34B) penetrates the first portion (26; [0020]).
Lin does not explicitly disclose a plurality of peripheral conductive lines (34B),
wherein each of the plurality of peripheral conductive lines (34B) is connected to a corresponding conductive contact of the second conductive contacts.
However, Kao teaches a magnetic memory device (FIG. 10; [0054]) comprising a plurality of peripheral conductive lines (330A; [0056]),
wherein each of the plurality of peripheral conductive lines (330A) is connected to a corresponding conductive contact (340A; [0056]) of the second conductive contacts (340A; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Claim 1 with the limitations taught by Kao to include distinct contact/line elements as a functionally equivalent means of predictably establishing electrical contact through an insulating layer to an underlying conductive line as taught by Kao ([0056]).
Claims 11-12 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kao.
Re Claim 11, Lin discloses a magnetic memory device (FIG. 6; [0020]-[0021]), comprising:
a plurality of conductive lines (12; [0012]) provided in a cell region (102; [0011]) and a peripheral region (104; [0012]);
a first insulating layer (10; [0011]) provided in the cell region (102; [0011]) and the peripheral region (104; [0011]), and surrounding the conductive lines (12; [0012]);
a second insulating layer (14, 26, in 102; [0014]) disposed on the first insulating layer (10) in the cell region (102; [0014]) to cover top surfaces of corresponding first conductive lines (12, in 102; [0014]) of the plurality of conductive lines (12; [0014]);
a plurality of data storage patterns (106; [0011]) disposed on the second insulating layer (14, 26) in the cell region (102; [0011]) and electrically connected to the corresponding first conductive lines (12, in 102; [0013]);
a plurality of insulating patterns (14, 26, in 104; [0014]) disposed on the first insulating layer (10) in the peripheral region (104; [0014]) on top surfaces of corresponding second conductive lines (12, in 104; [0014]) of the plurality of conductive lines (12; [0014]); and
a peripheral insulating layer (28; [0017]) disposed on the first insulating layer (10) in the peripheral region (104; [0017]) and between the plurality of insulating patterns (14, 26, in 104; [0017], due to the insulating patterns being recessed),
wherein the peripheral insulating layer (28) has a dielectric constant lower than a dielectric constant of the second insulating layer (14, 26, in 102) and a dielectric constant of the plurality of insulating patterns (14, 26, in 104; [0014]-[0017], silicon oxide in 28 lower than silicon nitride in 26).
Lin does not explicitly disclose wherein the device comprises a substrate including the cell region (102) and the peripheral region (104),
wherein the first insulating layer (10) is provided on the substrate.
However, Kao teaches a magnetic memory device (FIG. 10; [0054]) comprising wherein the device comprises a substrate (302, 320; [0054]) including the cell region (100A; [0013]) and the peripheral region (100B, 100C; [0013]),
wherein the first insulating layer (110; [0017]) is provided on the substrate (302, 320; [0054]),
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Lin with the limitations taught by Kao to include a substrate (Kao: 302, 320) underlying the device to allow for inclusion of transistors connected to the overlying device for controlling storage as taught by Kao ([0054]-[0055]).
Re Claim 12, Lin and Kao teach the magnetic memory device according to Claim 11, while Lin further teaches wherein the plurality of insulating patterns (14, 26, in 104) and the second insulating layer (14, 26, in 102) have different crystal structures from each other ([0014], silicon nitride in 26 in 102 has different structure than silicon oxide in 14 in 104 due to the different material constituent characteristics of nitrogen and oxygen).
Re Claim 14, Lin and Kao teach the magnetic memory device according to Claim 11, while Lin further teaches wherein a width of each of the plurality of insulating patterns (14, 26, in 104) in a first direction (left to right in FIG. 6; [0011], akin to width of P1 in FIG. Z1) is greater than or equal to a width of each of the plurality of conductive lines (12) in the first direction (left to right in FIG. 6; [0012], equal), and
the first direction (left to right in FIG. 6 is parallel to a top surface of the substrate ([0011], substrate taught by Kao, but top surface would be parallel to bottom surface of 10, 12 in Lin and therefore the established first direction in Lin).
Re Claim 15, Lin and Kao teach the magnetic memory device according to Claim 11, while Lin further teaches the device comprises a plurality of bottom electrode contacts (18; [0013]) provided between the plurality of data storage patterns (106) and the plurality of conductive lines (12; [0013]),
wherein the plurality of bottom electrode contacts (18) are connected to the plurality of data storage patterns (106), respectively ([0013]),
each bottom electrode contact (18) of the plurality of bottom electrode contacts (18) is connected to a corresponding conductive line (12) of the plurality of conductive lines (12; [0013]), and
a height of the plurality of bottom electrode contacts (18) is equal to a height of the of the plurality of insulating patterns (14, 26 combined, in 104; [0013]).
Re Claim 16, Lin and Kao teach the magnetic memory device according to Claim 11, while Lin further teaches wherein the second insulating layer (14, 26, in 102) has a recess region (R2, see FIG. Z2; [0011]), which is disposed between the plurality of data storage patterns (106; [0011]) and recessed toward the first substrate ([0011], underlying layers 10, 12), and
a lowermost portion of a top surface of the recess region (R2) of the second insulating layer (14, 26, in 102) is located at a level lower than top surfaces of the plurality of insulating patterns (14, 26, in 104; [0011]).
Re Claim 17, Lin discloses a magnetic memory device (FIG. 6; [0020]-[0021]), comprising:
a plurality of conductive lines (12; [0012]) provided in a cell region (102; [0011]) and a peripheral region (104; [0012]);
a first insulating layer (10; [0011]) provided in the cell region (102; [0011]) and the peripheral region (104; [0011]), surrounding the plurality of conductive lines (12; [0012]);
a second insulating layer (14, 26; [0014]) provided on the first insulating layer (10) in the cell region (102; [0014]) and the peripheral region (104; [0014]) to cover top surfaces of the plurality of conductive lines (12; [0014]); and
a plurality of data storage patterns (106; [0011]) disposed on the second insulating layer (14, 26) in the cell region (102; [0011]) and electrically connected to corresponding conductive lines (12, in 102; [0011]) of the plurality of conductive lines (12; [0013]),
wherein the second insulating layer (14, 26) in the peripheral region (104) comprises a first portion (P1, see FIG. Z1) covering top surfaces of the plurality of conductive lines (12) in the peripheral region (104; [0011]), and
the plurality of first portions (P1) have a crystal structure different from a crystal structure of the second insulating layer (14, 26) in the cell region (102; [0014], silicon nitride in 26 in P1 has different structure than silicon oxide in 14 in 102 due to the different material constituent characteristics of nitrogen and oxygen).
Lin does not explicitly disclose wherein the device comprises a substrate including the cell region (102) and the peripheral region (104),
wherein the first insulating layer (10) is provided on the substrate.
However, Kao teaches a magnetic memory device (FIG. 10; [0054]) comprising wherein the device comprises a substrate (302, 320; [0054]) including the cell region (100A; [0013]) and the peripheral region (100B, 100C; [0013]),
wherein the first insulating layer (110; [0017]) is provided on the substrate (302, 320; [0054]),
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Lin with the limitations taught by Kao to include a substrate (Kao: 302, 320) underlying the device to allow for inclusion of transistors connected to the overlying device for controlling storage as taught by Kao ([0054]-[0055]).
Re Claim 18, Lin and Kao teach the magnetic memory device according to Claim 17, while Lin further teaches wherein a width of the first portion (P1) in a first direction (left to right in FIG. 6; [0011]) is greater than or equal to a width of the plurality of conductive lines (12) in the first direction (left to right in FIG. 6; [0012], equal), and
the first direction (left to right in FIG. 6 is parallel to a top surface of the substrate ([0011], substrate taught by Kao, but top surface would be parallel to bottom surface of 10, 12 in Lin and therefore the established first direction in Lin).
Re Claim 19, Lin and Kao teach the magnetic memory device according to Claim 17, while Lin further teaches the device comprises a plurality of bottom electrode contacts (18; [0013]) provided between the plurality of data storage patterns (106) and the plurality of conductive lines (12; [0013]),
wherein the plurality of bottom electrode contacts (18) are connected to the plurality of data storage patterns (106), respectively ([0013]),
each of the plurality of bottom electrode contacts (18) is connected to a corresponding first conductive line (12, in 102) of the plurality of conductive lines (12; [0013]), and
a height of the plurality of bottom electrode contacts (18) is equal to a vertical thickness of the first portion (P1, 14, 26, combined; [0013]).
Re Claim 20, Lin and Kao teach the magnetic memory device according to Claim 17, while Lin further teaches wherein the second insulating layer (14, 26) in the peripheral region (104) has a recess region (P2, see FIG. Z1; [0011]), which is recessed toward the first substrate ([0011], underlying layers 10, 12), and
a lowermost portion of a top surface of the recess region (P2) is located at a level lower than top surfaces of the first portion (P1; [0011]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and Kao, as applied to Claim 12, further in view of Kuroda.
Re Claim 13, Lin and Kao teach the magnetic memory device according to Claim 12, but they do not explicitly disclose wherein the second insulating layer (14, 26, in 102) and the plurality of insulating patterns (14, 26, in 104) comprise a carbon nitride (CN), and
a fraction of a sp3 C-N bonding in the plurality of insulating patterns (14, 26, in 102) is greater than a fraction of a sp3 C-N bonding in the plurality of insulating patterns (14, 26, in 104).
Kuroda discloses a device (column 9, lines 1-4) comprising wherein the insulating layer/insulative patterns (23; column 9, lines 1-4) comprise a carbon nitride (CN) (column 9, lines 1-4).
By specifying the nitride layer 26 of Lin is carbon nitride with sp3 C-N bonding, the plurality of insulating patterns (14, 26, in 102) in Lin, specifically the layer 26 in 102, has a fraction of sp3 C-N bonding greater than a fraction of sp3 C-N bonding in the silicon oxide layer 14 of the plurality of insulating patterns (14, 26, in 104) (as silicon oxide would have none).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the magnetic memory device according to Claim 12 with the limitations taught by Kuroda to specify the nitride layer 26 of Lin is carbon nitride as a functionally equivalent material for a nitride layer providing insulation as taught by Kuroda (column 9, lines 1-4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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