DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 1 recites first and second staircase structures each including a plurality of division block structures in the second and third indented limitations, but then goes on to recite “adjacent division block structures”, “at least one of the division block structures”, “a plurality of staircases”, and “at least one of the staircases” in subsequent limitations which each creates a lack of clarity as to which staircase (which are each structures) or staircase structure and which division block structure (i.e. related to the first or the second staircase structures) is being referenced. Claim 3 recites “at least one of the plurality of steps of the second staircase structure” which creates a lack of clarity as to which steps are being referenced because the second staircase structure was not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 1. Claim 6 recites “adjacent staircases” which creates a lack of clarity as to which staircase or staircase structure is being referenced. Claim 7 recites “each staircase” which creates a lack of clarity as to which staircase or staircase structure is being referenced. Claim 8 recites “the plurality of staircases” and “each division block structure” which each creates a lack of clarity as to which staircase (which are structures) or staircase structure and which division block structure is being referenced. Claim 9 recites “adjacent division block structures” which creates a lack of clarity as to which division block structure is being referenced. Claim 10 recites “the plurality of steps in the first staircase structure and the second staircase structure” in the first limitation and “the plurality of steps” in the second limitation which creates a lack of clarity as to which steps are being referenced because the first and second staircase structures were not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 1. Claim 11 recites “a first staircase structure”, “a plurality of staircases”, and “at least one of the staircases” which creates a lack of clarity as to which staircases (which are structures) or staircase structure is being referenced. Claim 13 recites “at least one of the plurality of steps of the second staircase structure” in the third limitation which creates a lack of clarity as to which steps are being referenced because the second staircase structure was not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 11. Claim 15 recites “each one of the plurality of staircases includes a number (2X2-1) of steps” in the third limitation which creates a lack of clarity as to which steps are being referenced given that claim 11 introduced “at least one of the staircases includes a plurality of steps.” Claim 15 further recites “the plurality of steps in the first staircase structure and the second staircase structure” in the second to last limitation and “the plurality of steps” in the last limitation which creates a lack of clarity as to which steps are being referenced because the first and second staircase structures were not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 11. Claim 16 recites “a first staircase structure”, “a plurality of staircases”, and “at least one of the staircases” which creates a lack of clarity as to which staircases (which are structures) or staircase structure is being referenced. Claim 18 recites “at least one of the plurality of steps of the first staircase structure” in the third limitation which creates a lack of clarity as to which steps are being referenced because the first staircase structure was not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 16. Claim 20 recites “each one of the plurality of staircases includes a number (2X2-1) of steps” in the third limitation which creates a lack of clarity as to which steps are being referenced given that claim 16 introduced “at least one of the staircases includes a plurality of steps.” Claim 20 further recites “the plurality of steps in the first staircase structure and the second staircase structure” in the second to last limitation and “the plurality of steps” in the last limitation which creates a lack of clarity as to which steps are being referenced because the first and second staircase structures were not previously introduced as comprising a “plurality of steps” but rather only “at least one of the staircases” was previously introduced as comprising a “plurality of steps” in claim 16.
Dependent claims 2-10, 12-15 and 17-20 depend from independent claims 1, 11 and 16, respectively, and so claims 2-10, 12-15 and 17-20 are similarly rejected at least on the same grounds as claims 1, 11 and 16 in this regard. Despite the numerous instances of the claim set lacking clarity, Examiner will provide examination of claims 1-20 as best understood.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20, as best understood, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 and 6-7 of U.S. Patent No. 11,069,705 B2 to Zhang et al. (hereinafter “Zhang”) in view of US 2014/0159127 A1 to Lee et al. (hereinafter “Lee”).
Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation of claims 1-20 are claimed in claims 1-4 and 6-7 of Zhang except for those limitations related to a “bottom select gate staircase structure” in claims 1-2, 12-13, 16 and 19 of the instant application. However, each of those limitations related to a bottom select gate staircase structure is disclosed by the first and second staircase structures, cell structure C, and top and bottom gate conductive layers of 3D memory cell of Fig. 1 and paragraphs [0020]-[0026] of Lee. Further, claim 1 of Zhang already discloses a top select gate staircase structure which strongly suggests the presence of a bottom select gate staircase on its own.
Zhang and Lee are considered to be analogous to the claimed invention because they are in the same field of 3D memory devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate the teachings of Lee in order to potentially provide a bottom portion equivalent of the top portion in order to provide a symmetric memory device for improved manufacturing process uniformity, reduced die area, and higher bit density.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20, as best understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee.
Regarding claim 1, Lee discloses a three-dimensional (3D) memory device, comprising:
a plurality of channel structures extending along a vertical direction (3D memory cell having cell structures C extending along vertical direction; Figs. 1 and 5; paragraphs [0020]-[0026], [0062]);
a first staircase structure including a plurality of division block structures arranged along a first direction on a first side of the channel structures (first staircase structure of 3D memory cell including a plurality of iterative stepped structures arranged along first direction on first side of cell structures C; Fig. 1);
a second staircase structure including a plurality of division block structures arranged along the first direction on a second side of the channel structures (second staircase structure of 3D memory cell including a plurality of iterative stepped structures arranged along first direction on first side of cell structures C; Fig. 1);
a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction (top gate conductive layers disposed between cell structures C and first staircase structure in second direction; Fig. 1); and
a bottom select gate staircase structure, the second staircase structure is disposed between the channel structures and the bottom select gate staircase structure in the second direction (second staircase structure of 3D memory cell disposed between cell structure C and bottom gate conductive layers in second direction; Fig. 1; paragraphs [0020]-[0026]), wherein a first vertical offset defines a boundary between adjacent division block structures (first structural vertical offset defines boundary between adjacent iterative stepped structures; Fig. 1); at least one of the division block structures includes a plurality of staircases arranged along the second direction (iterative stepped structures include plurality of staircases arranged along second direction; Fig. 1); at least one of the staircases includes a plurality of steps arranged along the first direction (each staircase includes steps in first direction; Fig. 1); and the first direction, the second direction, and the vertical direction are perpendicular to each other (first, second and vertical directions are perpendicular to one another; Fig. 1).
Regarding claim 2, Lee discloses the 3D memory device of claim 1, wherein: the top select gate staircase structure is located on a first vertical side of the first staircase structure in the vertical direction (top gate conductive layers located on first vertical side of first staircase in vertical direction; Fig. 1); the bottom select gate staircase structure is located on a second vertical side of the second staircase structure in the vertical direction (bottom gate conductive layers located on second vertical side of second staircase in vertical direction; Fig. 1); and the first vertical side and the second vertical side are opposite to each other in the vertical direction (first and second vertical sides are opposite one another in vertical direction; Fig. 1).
Regarding claim 3, Lee discloses the 3D memory device of claim 2, wherein at least one of the plurality of steps of the second staircase structure is located on the first vertical side of the first staircase structure in the vertical direction (one of steps of second staircase is on first vertical side of first staircase in vertical direction; Fig. 1).
Regarding claim 4, Lee discloses the 3D memory device of claim 1, wherein: the first staircase structure and the second staircase structure include a plurality of dielectric/conductive layer pairs; each step includes a dielectric/conductive layer pair (each step of staircase may include an oxide layer and a conductive layer; Fig. 2B; paragraphs [0036]-[0038]); and the top select gate staircase structure includes a number X2 of steps arranged along the second direction (top conductive layers include a number of steps arranged in second direction; Fig. 1).
Regarding claim 5, Lee discloses the 3D memory device of claim 4, wherein a second vertical offset between the plurality of division block structures in the first staircase structure and the plurality of division block structures in the second staircase structure equals X2 times a thickness of one step (second structural vertical offset between iterative stepped structures of first and second staircases may equal the thickness of the top conductive layers; Figs. 1 and 2B).
Regarding claim 6, Lee discloses the 3D memory device of claim 4, wherein a third vertical offset between adjacent staircases equals 2X2 times a thickness of one step (third structural vertical offset between first and second staircases may equal double the thickness of the top conductive layers; Figs. 1 and 2B).
Regarding claim 7, Lee discloses the 3D memory device of claim 4, wherein each staircase includes a number (2X2-1) of steps distributed symmetrically in X2 levels (first and second staircases may include two times less one of the number of steps in the top conductive layers and may further be defined to be distributed symmetrically in a number of levels equal to the number of steps in the top conductive layers; Figs. 1 and 2B; paragraph [0032]).
Regarding claim 8, Lee discloses the 3D memory device of claim 4, wherein: a number of the plurality of division block structures in each of the first staircase structure and the second staircase structure is X1; and a number of the plurality of staircases in each division block structure is X3 (number of iterative stepped structures of the first and second staircases may be the same and there exists a number of staircases in each stepped structure; Figs. 1 and 2B).
Regarding claim 9, Lee discloses the 3D memory device of claim 8, wherein the first vertical offset between adjacent division block structures equals 2X2X3 times a thickness of one step (first structural vertical offset between iterative stepped structures may equal two times a number steps in the top conductive layers times a number of staircases in each stepped structure times a thickness of one step; Figs. 1 and 2B; paragraph [0032]).
Regarding claim 10, Lee discloses the 3D memory device of claim 8, wherein: a total number of the plurality of steps in the first staircase structure and the second staircase structure is 2X1(2X2-1)X3; and the plurality of steps are distributed in a number of 2X1X2X3 different levels (first and second staircases may include an arbitrary number of steps which may be defined to be distributed in an arbitrary number of levels; Figs. 1 and 2B; paragraph [0032]).
Regarding claim 11, Lee discloses a three-dimensional (3D) memory device, comprising: a plurality of channel structures extending along a vertical direction (3D memory cell having cell structures C extending along vertical direction; Figs. 1 and 5; paragraphs [0020]-[0026], [0062]); a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures (first staircase structure of 3D memory cell including a plurality of iterative stepped structures arranged along first direction on first side of cell structures C; Fig. 1); and a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction that is different from the first direction (top gate conductive layers disposed between cell structures C and first staircase structure in second direction; Fig. 1), wherein at least one of the division block structures includes a plurality of staircases arranged along the second direction (iterative stepped structures include plurality of staircases arranged along second direction; Fig. 1), and at least one of the staircases includes a plurality of steps arranged along the first direction (each staircase includes steps in first direction; Fig. 1).
Regarding claim 12, Lee discloses the 3D memory device of claim 11, further comprising: a bottom select gate staircase structure, wherein the channel structures are disposed between the top select gate staircase structure and the bottom select gate staircase structure in the second direction (cell structure C disposed between top gate conductive layers and bottom gate conductive layers in a second direction; Fig. 1; paragraphs [0020]-[0026]).
Regarding claim 13, Lee discloses the 3D memory device of claim 12, further comprises a second staircase structure disposed between the channel structures and the bottom select gate staircase structure in the second direction (second staircase disposed between cell structure C and bottom gate conductive layers; Fig. 1; paragraphs [0020]-[0026]), wherein the top select gate staircase structure is located on a first vertical side of the first staircase structure in the vertical direction (top gate conductive layers located on first vertical side of first staircase in vertical direction; Fig. 1); and at least one of the plurality of steps of the second staircase structure is located on the first vertical side of the first staircase structure in the vertical direction (one of steps of second staircase is on first vertical side of first staircase in vertical direction; Fig. 1).
Regarding claim 14, Lee discloses the 3D memory device of claim 13, wherein: the top select gate staircase structure includes a number X2 of steps arranged along the second direction (top conductive layers include a number of steps arranged in second direction; Fig. 1); a number of the plurality of division block structures in each of the first staircase structure and the second staircase structure is X1; and a number of the plurality of staircases in each division block structure is X3 (number of iterative stepped structures of the first and second staircases may be the same and there exists a number of staircases in each stepped structure; Figs. 1 and 2B).
Regarding claim 15, Lee discloses the 3D memory device of claim 14, wherein: a second vertical offset between the plurality of division block structures in the first staircase structure and the plurality of division block structures in the second staircase structure equals X2 times a thickness of one step (second structural vertical offset between iterative stepped structures of first and second staircases may equal the thickness of the top conductive layers; Figs. 1 and 2B); a third vertical offset between adjacent staircases equals two 2X2 times the thickness of one step (third structural vertical offset between first and second staircases may equal double the thickness of the top conductive layers; Figs. 1 and 2B); each one of the plurality of staircases includes a number (2X2-1) of steps distributed symmetrically in X2 levels (first and second staircases may include two times less one of the number of steps in the top conductive layers and may further be defined to be distributed symmetrically in a number of levels equal to the number of steps in the top conductive layers; Figs. 1 and 2B; paragraph [0032]); a first vertical offset between adjacent division block structures equals 2X2X3 times the thickness of one step (first structural vertical offset between iterative stepped structures may equal two times a number steps in the top conductive layers times a number of staircases in each stepped structure times a thickness of one step; Figs. 1 and 2B; paragraph [0032]); a total number of the plurality of steps in the first staircase structure and the second staircase structure is 2X1(2X2-1)X3; and the plurality of steps are distributed in a number of 2X1X2X3 different levels (first and second staircases may include an arbitrary number of steps which may be defined to be distributed in an arbitrary number of levels; Figs. 1 and 2B; paragraph [0032]).
Regarding claim 16, Lee discloses a three-dimensional (3D) memory device, comprising: a plurality of channel structures extending along a vertical direction (3D memory cell having cell structures C extending along vertical direction; Figs. 1 and 5; paragraphs [0020]-[0026], [0062]); a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures (first staircase structure of 3D memory cell including a plurality of iterative stepped structures arranged along first direction on first side of cell structures C; Fig. 1); and a bottom select gate staircase structure, the first staircase structure is disposed between the channel structures and the bottom select gate staircase structure in a second direction that is different from the first direction (first staircase structure of 3D memory cell disposed between cell structure C and bottom gate conductive layers; Fig. 1; paragraphs [0020]-[0026]), wherein at least one of the division block structures includes a plurality of staircases arranged along the second direction (iterative stepped structures include plurality of staircases arranged along second direction; Fig. 1), and at least one of the staircases includes a plurality of steps arranged along the first direction (each staircase includes steps in first direction; Fig. 1).
Regarding claim 17, Lee discloses the 3D memory device of claim 16, further comprising: a top select gate staircase structure, wherein the channel structures are disposed between the top select gate staircase structure and the first staircase structure in the second direction (cell structures C disposed between top gate conductive layers and first staircase structure in second direction; Fig. 1).
Regarding claim 18, Lee discloses the 3D memory device of claim 17, further comprises a second staircase structure, wherein the top select gate staircase structure is disposed between the second staircase structure and the channel structures in the second direction (top gate conductive layers disposed between cell structures C and second staircase structure in second direction; Fig. 1); the top select gate staircase structure is located on a first vertical side of the second staircase structure in the vertical direction (top gate conductive layers located on first vertical side of second staircase in vertical direction; Fig. 1); and at least one of the plurality of steps of the first staircase structure is located on the first vertical side of the second staircase structure in the vertical direction (one of steps of first staircase is on first vertical side of second staircase in vertical direction; Fig. 1).
Regarding claim 19, Lee discloses the 3D memory device of claim 16, wherein: the bottom select gate staircase structure includes a number X2 of steps arranged along the second direction (top conductive layers include a number of steps arranged in second direction; Fig. 1); a number of the plurality of division block structures in each of the first staircase structure and the second staircase structure is X1; and a number of the plurality of staircases in each division block structure is X3 (number of iterative stepped structures of the first and second staircases may be the same and there exists a number of staircases in each stepped structure; Figs. 1 and 2B).
Regarding claim 20, Lee discloses the 3D memory device of claim 19, wherein: a second vertical offset between the plurality of division block structures in the first staircase structure and the plurality of division block structures in the second staircase structure equals X2 times a thickness of one step (second structural vertical offset between iterative stepped structures of first and second staircases may equal the thickness of the top conductive layers; Figs. 1 and 2B); a third vertical offset between adjacent staircases equals two 2X2 times the thickness of one step (third structural vertical offset between first and second staircases may equal double the thickness of the top conductive layers; Figs. 1 and 2B); each one of the plurality of staircases includes a number (2X2-1) of steps distributed symmetrically in X2 levels (first and second staircases may include two times less one of the number of steps in the top conductive layers and may further be defined to be distributed symmetrically in a number of levels equal to the number of steps in the top conductive layers; Figs. 1 and 2B; paragraph [0032]); a first vertical offset between adjacent division block structures equals 2X2X3 times the thickness of one step (first structural vertical offset between iterative stepped structures may equal two times a number steps in the top conductive layers times a number of staircases in each stepped structure times a thickness of one step; Figs. 1 and 2B; paragraph [0032]); a total number of the plurality of steps in the first staircase structure and the second staircase structure is 2X1(2X2-1)X3; and the plurality of steps are distributed in a number of 2X1X2X3 different levels (first and second staircases may include an arbitrary number of steps which may be defined to be distributed in an arbitrary number of levels; Figs. 1 and 2B; paragraph [0032]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2018/0102281 A1 to Yang, US 2018/0174661 A1 to Kim et al., and US 2018/0294224 A1 to Yang each discloses stepped 3D memory cells and related structures arranged similar to the presently claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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