CTNF 18/608,440 CTNF 87419 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Teh et al. (PGPUB 20180239738), hereinafter as Teh . Regarding claim 1 , Teh teaches a system, comprising: a die comprising: a first set of physical layer (PHY) blocks arranged in a first column (Fig 4, IO modules 402 arranged in a column, in y direction), wherein the first column extends along a side of the die; and a second set of PHY blocks arranged in a second column adjacent to the first column (Fig 4, a second column of 402 modules adjacent and the first column), wherein the first set of PHY blocks include a first PHY block, the second set of PHY blocks include a second PHY block, and the first PHY block and the second PHY block share one or more clock resources (Fig 5A, Q3 has many 402s, line in 2 column as in Fig 4, and sharing Clk3). Regarding claim 17 , Teh teaches a system, comprising: a die including physical layer (PHY) blocks arranged in at least two columns, wherein a first column of the at least two columns extends along a side of the die, a second column of the at least two columns is adjacent to the first column (Fig 4), the PHY blocks include a first PHY block in the first column and a second PHY block in the second column, and the first PHY block and the second PHY block share one or more clock resources (Fig 5, reasoning in the rejection of claim 1 applies) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2-12, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teh . Regarding claim 2 , Teh teaches a first locked loop (PLL) in the first PHY block, wherein the first PLL is configured to generate a first clock signal (Fig 5A, Clk3); and a second PLL in the second PHY block, wherein the second PLL is configured to generate a second clock signal (Fig 5A, Clk4) having a different frequency than the first clock signal ([0071] clock signals of varying frequencies); except a separate second PLL. It would have been obvious to one having ordinary skill int eh art at the time the invention was made to have two PLL circuit instead one PLL circuit, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 SPQ 177, 179. Regarding claim 3 , Teh teaches a first input-output (IO) circuit; a second IO circuit (Fig 4, 402 I/O modules); and a first multiplexer (Fig 5A, 516 and 518) having a first input coupled to the first PLL, a second input coupled to the second PLL, and an output coupled to the first IO circuit and the second IO circuit. Regarding claim 4 , Teh teaches each of the first IO circuit and the second IO circuit includes at least eight transmitters configured to transmit at least eight bits in parallel (It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have more than 8 transistors and transmit more than 8 bits in parallel, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). Regarding claim 5 , argument used in rejection of claim 4 applies. Regarding claim 6/8 , Teh teaches a system as in rejection of claim 3, except a third/fourth IO circuits, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Regarding claim 7 , Teh teaches a first input-output (IO) circuit; a second IO circuit; and a multiplexer having a first input coupled to the first PLL, a second input coupled to the second PLL, and an output coupled to the first IO circuit and the second IO circuit (Fig 5A, the circuit functions the same way although arrangement/grouping is different, which is not allowable feature as indicated by case law, In re Japikse, 86 USPQ 70. Regarding claim 9 , Teh teaches the one or more clock resources comprise: a first locked loop (PLL) configured to generate a first clock signal; and a second PLL configured to generate a second clock signal having a different frequency than the first clock signal ([0071]). Regarding claim 10 , argument used in rejection of claim 7 applies. Regarding claim 11 , Teh teaches the first PLL and the second PLL are located between a first portion of the first set of PHY blocks and a second portion of the first set of PHY blocks (Fig 5A). Regarding claim 12 , the examiner is taking note that it is well known that a package; and bumps electrically coupling the first PHY block and the second PHY block to pins on the package. Regarding claim 15 , Teh teaches a substrate, wherein the package is mounted on the substrate; and a memory device mounted on the substrate, wherein the memory device is electrically coupled to the pins on the package ([0003]). Regarding claim 16 , Teh teaches each of the first column and the second column extends in a first direction (Fig 4, 402s, in y direction); the first column has a first width in a second direction perpendicular to the first direction; the second column has a second width in the second direction (Fig 4, the width is in x direction); and a distance between the first column and the second column in the second direction is less than each of the first width and the second width (Fig 4, show the gap is less than the width of the column) . 07-21-aia AIA Claim (s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over The, in view of Teh (PGPUB 20160098061), hereinafter as T2 . Regarding claim 13 , Teh teaches a system of claim 12, T2 teaches the bumps include one or more supply bumps overlapping the first PHY block and the second PHY block (Fig 5). Since T2 and Teh are both from the same field of memory device, the purpose disclosed by T2 would have been recognized in the pertinent art of Teh. It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to arrange bumps as in T2 into the device of Teh for the purpose of connecting circuits between inside and outside of the die. Regarding claim 14 , T2 teaches the bumps include one or more ground bumps overlapping the first PHY block and the second PHY block (Fig 5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIN HUANG/ Primary Examiner, Art Unit 2827 Application/Control Number: 18/608,440 Page 2 Art Unit: 2827 Application/Control Number: 18/608,440 Page 3 Art Unit: 2827 Application/Control Number: 18/608,440 Page 4 Art Unit: 2827 Application/Control Number: 18/608,440 Page 5 Art Unit: 2827 Application/Control Number: 18/608,440 Page 6 Art Unit: 2827
Prosecution Insights