Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 21st, 2026 has been entered.
Response to Amendment
The amendment filed April 21st, 2026 has been entered. Claims 1-11 and 13-21 are pending in this application. Claim 12 has been canceled. Independent claims 1 and 20 have been amended to teach communicating to a host device that match bit or error status of the first copy of the codeword hat is based at least in part on the match bit. New claim 21 has been added to teach that the match bit comprises a single bit. The amendments have been fully considered but are not persuasive because the cited prior art teaches or suggests communicating error information derived from comparison operation, to a host device. Accordingly, the amendments do not overcome the rejection set forth below.
Response to Arguments
Applicant's arguments filed April 21st, 2026 have been fully considered but they are not persuasive.
Applicant argues that the prior rejection failed to identify where the cited references teach or suggest communicating to a host device the match bit or an error status based on the match bit, and failed to provide sufficient reasoning why this information would have been communicated.
The argument ahs been considered but is not persuasive. As set forth in the rejection below, Freikorn et al. (US 10,496,484), hereinafter Freikorn, teaches comparing information associated with first and second copies of data and determining the data’s validity based on the results of a parity comparison operation. Selinger (US 2011/0041005) teaches generating error detection information, determining whether the compared error detection information matches, and communicating a status indication to a host device when an error has been identified. A person of ordinary skill in the art would have recognized that the comparison results of Freikorn could be communicated using the status communication of Selinger.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Freikorn, in view of Selinger.
Regarding claim 1, Freikorn teaches a method, comprising:
reading, from memory, a first copy of a codeword and a second copy of the codeword (Freikorn, Fig. 1 teaches data 181 & data copy 182; Fig. 3, block 304);
comparing, based at least in part on reading the first copy of the codeword and the second copy of the codeword, a portion of the first copy of the codeword with a portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”);
generating, based at least in part on the comparison, a match bit that indicates whether the portion of the first copy of the codeword matches the portion of the second copy of the codeword (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid; the reference does not explicitly teach a “match bit”, however the parity comparison result inherently corresponds to some sort of match indication or status bit/flag); and
Freikorn fails to teach communicating, to a host device: the match bit, or an error status of the first copy of the codeword that is based at least in part on the match bit.
However, Selinger, in an analogous art, teaches communicating, to a host device: the match bit, or an error status of the first copy of the codeword that is based at least in part on the match bit (Selinger, Abstract, lines 5-12, “a controller receives a command from a host, retrieves data from flash memory, analyzes the retrieved data for errors, and transmits status information to the host, wherein the status information comprises information based on a result of the error analysis, such as a read error. Alternatively, the controller stores the status information and transmits an error indicator to the host identifying that the status information regarding the error is available in memory”).
Freikorn and Selinger are both considered to be analogous to the claimed invention because both are in the same field of error detection and reliability within memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of communicating match information derived from parity comparisons, or an error status based on the parity comparison match information, to a host device.
The suggestion/motivation for doing so would be to help facilitate host reliability and improve the overall integrity of the memory system.
Regarding claim 2, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: receiving, from the host device, a read command for a set of data, wherein a first set of data bits in the first copy of the codeword is representative of the set of data, and wherein a second set of data bits in the second copy of the codeword is representative of the set of data; and communicating, to the host device in response to the read command, the first set of data bits in the first copy of the codeword based at least in part on the error status of the first copy of the codeword (Freikorn, col. 2, lines 35-37, “FIG.1 depicts an illustrative example of a system 100 that includes a data storage device 102 and an access device 170 [e.g., a host device or another device]”; col. 4, lines 36-43, "The access device 170 may issue one or more commands to the data storage device 102, such as one or more requests to erase data, read data from, or write data to the memory device 103 of the data storage device 102. For example, the access device 170 may be configured to provide data, such as data 180, to be stored at the memory device 103 or to request data to be read from the memory device 103").
Regarding claim 3, the combination of Freikorn in view of Selinger teaches the method of claim 1, wherein the portion of the first copy of the codeword comprises first parity bits and the portion of the second copy of the codeword comprises second parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180").
Regarding claim 4, the combination of Freikorn in view of Selinger teaches the method of claim 1, wherein the portion of the first copy of the codeword comprises a first set of data bits and the portion of the second copy of the codeword comprises a second set of data bits (Freikorn, Fig. 1, data 181 & data copy 182).
Regarding claim 5, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: comparing, based at least in part on reading the first copy of the codeword and the second copy of the codeword, a second portion of the first copy of the codeword with a second portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”); and
generating, based at least in part on comparing the second portion of the first copy of the codeword with the second portion of the second copy of the codeword, a second match bit that indicates whether the second portion of the first copy of the codeword matches the second portion of the second copy of the codeword, wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid). Freikorn does not explicitly teach generating a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform the comparison operations on additional portions of the stored data/codewords and generate a second match indicator for the additional comparison, as generating separate comparison indicators for portions of data is a known technique in redundancy validation within memory systems.
Regarding claim 6, the combination of Freikorn in view of Selinger teaches the method of claim 5, wherein the portion of the first copy of the codeword comprises a first set of data bits, the portion of the second copy of the codeword comprises a second set of data bits, the second portion of the first copy of the codeword comprises first parity bits, and the second portion of the second copy of the codeword comprises second parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180"). It would have been obvious to perform separate comparison operations on both the data bit and parity bit portions of the first and second copies of the codeword in order to improve the reliability of codeword verification.
Regarding claim 7, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: decoding the first copy of the codeword and the second copy of the codeword, wherein the portion of the first copy of the codeword is compared with the portion of the second copy of the codeword based at least in part on decoding the first copy of the codeword and the second copy of the codeword; and generating an error detection bit for the first copy of the codeword based at least in part on decoding the first copy of the codeword, wherein the error status of the first copy of the codeword is determined based at least in part on the error detection bit (Freikorn, col. 10, lines 17-20, "Validating the data copy 182 may include the encoder 154 (or the encoder 142) accessing the data copy 182 at the volatile memory 144 and processing the data copy 182 to generate the parity 195").
Regarding claim 8, the combination of Freikorn in view of Selinger teaches the method of claim 7, further comprising: correcting an error in the first copy of the codeword based at least in part on decoding the first copy of the codeword, wherein the portion of the first copy of the codeword is compared with the portion of the second copy of the codeword after correcting the error (Freikorn, col. 9, lines 19-23, "The ECC engine 158 may include one or more decoders configured to decode data read from the non-volatile memory 104 to detect and correct, up to an error correction capability of the ECC scheme, any bit errors that may be present in the data").
Regarding claim 9, the combination of Freikorn in view of Selinger teaches the method of claim 1, further comprising: decoding the first copy of the codeword and the second copy of the codeword (Freikorn, Fig. 1, bit error detector 152 performs error detection operations on the stored data copies; error detection operations include decoding) concurrently (Freikorn, Fig. 1 teaches the bit error detector 152 and comparator 156 integrated into the data path protection circuit 148; Freikorn does not explicitly teach “concurrently”, but the integrated bit error detector and comparator suggests parallel operations during the same verification flow) with comparing the portion of the first copy of the codeword with the portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”); and generating an error detection bit for the first copy of the codeword based at least in part on decoding the first copy of the codeword (Freikorn, Fig. 1, bit error detector 152; col. 8, lines 48-52, “the bit error detector 152 is configured to combine the data 184 and the parity 194 into a data word and to process the data word to generate a result [e.g., a syndrome] that indicates whether any bit errors were detected in the data word”), wherein the error status of the first copy of the codeword is determined based at least in part on the error detection bit (Freikorn, Fig. 2 teaches whether the data copy is valid/not valid based on error detection parity comparison bits).
Claim 20 is a memory system with limitations similar to the method of claim 1, and is rejected under the same rationale.
Regarding claim 21, the combination of Freikorn in view of Selinger teaches the method of claim 1, wherein the match bit comprises a single bit (Selinger, para. [0072], lines 11-15, “… a status bit 806, which can be padded to two or more bytes [accordingly, "bit" as used in the claims, can refer to a single bit or to one or more bits, such as one or more bytes). This status bit 806 may be a binary success or failure indication for use by the host 720”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Freikorn to incorporate the teachings of Selinger by including the functionality of the match bit being represented by a single bit.
The suggestion/motivation for doing so would be to provide an efficient way of communicating the outcome of an error detection operation.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Freikorn in view of Selinger, as applied to claim 1 above, and further in view of Tian et al. (US 2015/0121132), hereinafter Tian.
Regarding claim 10, the combination of Freikorn in view of Selinger teaches the method of claim 1, but fails to teach further comprising: generating, based at least in part on reading the first copy of the codeword, a first error detection bit that indicates whether an error has been detected in the first copy of the codeword, wherein the error status of the first copy of the codeword is based at least in part on the first error detection bit; and generating, based at least in part on reading the second copy of the codeword, a second error detection bit that indicates whether an error has been detected in the second copy of the codeword, wherein an error status of the second copy of the codeword is based at least in part on the match bit and the second error detection bit.
However, Tian, in an analogous art, teaches further comprising: generating, based at least in part on reading the first copy of the codeword, a first error detection bit that indicates whether an error has been detected in the first copy of the codeword, wherein the error status of the first copy of the codeword is based at least in part on the first error detection bit; and generating, based at least in part on reading the second copy of the codeword, a second error detection bit that indicates whether an error has been detected in the second copy of the codeword, wherein an error status of the second copy of the codeword is based at least in part on the match bit and the second error detection bit (Tian, para. [0030], lines 1-4, "Respective parity values of the first and second copies of the data are generated (208). For example, parity computing circuits 120 and 122 (FIG. 1) determine the respective parity values of the first and second copies of the data").
Freikorn, Selinger, and Tian are considered to be analogous to the claimed invention because they are in the same field of error detection and correction in memory systems and/or devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Freikorn in view of Selinger to incorporate the teachings of Tian by including the functionality of generating first and second error detection bits, with error statuses that are both based in part on match bits & error detection bits of the first and second copies of the codeword.
The suggestion/motivation for doing so would be to flag or identify whether an error is present in the data, which is a common practice in the field of error detection & correction.
Regarding claim 11, the combination of Freikorn in view of Blevins, further in view of Selinger, teaches the method of claim 10, further comprising: selecting between the first copy of the codeword and the second copy of the codeword for communication to the host device based at least in part on the error status of the first copy of the codeword and the error status of the second copy of the codeword (Tian, para. [0031], lines 1-9, "The respective parity values of the first and second copies of the data are compared (212) to the majority value of the stored copies of the parity value ( e.g., using the selection circuit 126, FIG. 1). Based on the comparing, a selection is made (214) between the first and second copies of the data. In some embodiments, making this selection includes generating a selection signal [e.g., as provided on output 130 of the selection circuit 126, FIG. 1] that specifies a selected one of the first and second copies of the data").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Freikorn in view of Selinger to incorporate the teachings of Tian by including the functionality of selecting between a first and second codeword copy for communication to a host, based at least in part on the error statuses of the codeword copies.
The suggestion/motivation for doing so would be to ensure the correct codeword is communicated to the host, which is a common practice in the field of error detection & correction.
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Selinger in view of Freikorn.
Regarding claim 13, Selinger teaches a method, comprising:
transmitting a read command for a set of data that is associated with a codeword (Selinger, Fig. 6, step 610 & 620);
receiving, based at least in part on transmitting the read command, a match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit); and
determining an error status based at least in part on the match bit (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”).
Selinger fails to teach determining whether a first copy of the codeword matches a portion of a second copy of the codeword and the error-status determination being based at least in part on the match bit of the first copy of the codeword.
However, Freikorn, in an analogous art, teaches determining whether a first copy of the codeword matches a portion of a second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”) and the error-status determination being based at least in part on the match bit of the first copy of the codeword (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid; the reference does not explicitly teach a “match bit”, however the parity comparison result inherently corresponds to some sort of match indication or status bit/flag).
Selinger and Freikorn are both considered to be analogous to the claimed invention because both are in the same field of same field of error detection and reliability within memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger’s teachings of a comparison result and error status determination to incorporate the teachings of Freikorn by including the functionality of redundant copy comparison.
The suggestion/motivation for doing so would improve the system’s ability to identify errors.
Regarding claim 14, the combination of Selinger in view of Freikorn teaches the method of claim 13, further comprising: receiving, based at least in part on transmitting the read command, a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether a second portion of the first copy of the codeword matches a second portion of the second copy of the codeword (Freikorn, Fig. 3, block 306 teaches an operation that includes “comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data”; Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger to incorporate the teachings of Freikorn by including the functionality of performing an additional comparison and generating corresponding comparison results.
The suggestion/motivation for doing so would be to allow for a more granular level of data verification.
Regarding claim 15, the combination of Selinger in view of Freikorn teaches the method of claim 14, wherein the portion of the first copy of the codeword comprises a first set of data bits, the portion of the second copy of the codeword comprises a second set of data bits, the second portion of the first copy of the codeword comprises a first set of parity bits, and the second portion of the second copy of the codeword comprises a second set of parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192; col. 6, lines 26-31, "For example, prior to sending the data 180 to the data storage device 102, the access device 170 may process the data 180 to generate a parity 190. The parity 190 includes redundancy data [e.g., a checksum, one or more parity bits, a repetition code, or a hash value, as illustrative, non-limiting examples] that is based on the data 180").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger to incorporate the teachings of Freikorn by including the functionality of redundant codeword copies that contain data bit and parity bit portions.
The suggestion/motivation for doing so would be to improve the reliability of codeword verification.
Regarding claim 16, the combination of Selinger in view of Freikorn teaches the method of claim 13, further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), an error detection bit that indicates whether a memory device detected an error in the first copy of the codeword (Selinger, Fig. 6, step 620), wherein the error status is determined based at least in part on the error detection bit (Selinger, Fig. 6, steps 630 through 670).
Regarding claim 17, the combination of Selinger in view of Freikorn teaches the method of claim 13, wherein the portion of the first copy of the codeword comprises a first set of data bits and the portion of the second copy of the codeword comprises a second set of data bits (Freikorn, Fig. 1, data 181 & data copy 182), the method further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether a first set of parity bits in the first copy of the codeword matches a second set of parity bits in the second copy of the codeword (Freikorn, Fig. 1, parity 191 & parity copy 192 combined with Selinger’s teachings of match/non-match determination [Selinger, Fig. 6, steps 630 through 670]), wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger to incorporate the teachings of Freikorn by including the functionality of performing an additional comparison and generating corresponding comparison results.
The suggestion/motivation for doing so would be to allow for a more granular level of data verification.
Regarding claim 18, the combination of Selinger in view of Freikorn teaches the method of claim 13, wherein the portion of the first copy of the codeword comprises a first set of parity bits and the portion of the second copy of the codeword comprises a second set of parity bits (Freikorn, Fig. 1, parity 191 & parity copy 192), the method further comprising: receiving, based at least in part on transmitting the read command (Selinger, Fig. 6, step 618), a second match bit (Selinger, Fig. 6, steps 630 through 670; the result from the comparison at step 640 equates to a match bit) that indicates whether the first set of parity bits in the first copy of the codeword matches the second set of parity bits in the second copy of the codeword (Freikorn, Fig. 1, parity 191 & parity copy 192 combined with Selinger’s teachings of match/non-match determination [Selinger, Fig. 6, steps 630 through 670]), wherein the error status of the first copy of the codeword is determined based at least in part on the second match bit (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”). The references do not explicitly teach receiving a second match bit corresponding to a second comparison between second portions of the first and second copies of the codeword, however it would have been obvious to one of ordinary skill in the art to perform an additional comparison on an additional portion of data and generate a second comparison result for separate portions of the data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger to incorporate the teachings of Freikorn by including the functionality of performing an additional comparison and generating corresponding comparison results.
The suggestion/motivation for doing so would be to allow for a more granular level of data verification.
Regarding claim 19, the combination of Selinger in view of Freikorn teaches the method of claim 13, further comprising: receiving the set of data based at least in part on transmitting the read command (Selinger, Fig. 6, step 610 & 620); and determining that the set of data is error-free (Selinger, Fig. 6, step 640) based at least in part on the error status (Selinger, para. [0065], lines 23-25, “If the correction does not succeed, a signal can be sent to the host 420 indicating that a storage error occurred”) of the first copy of the codeword (Freikorn, Fig. 2 teaches parity comparison to determine if the data and data copies are valid/non-valid; the reference does not explicitly teach a “match bit”, however the parity comparison result inherently corresponds to some sort of match indication or status bit/flag).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Selinger’s teachings of a comparison result and error status determination to incorporate the teachings of Freikorn by including the functionality of redundant copy comparison.
The suggestion/motivation for doing so would improve the system’s ability to identify errors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 2018/0210786) teaches comparing read data with reference data to identify errors, and generates information corresponding to the comparison.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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