Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Regarding claim 8, the phrase “wherein selectively removing the bilayer hardmask from the first region of the substrate further comprises” should be -- wherein selectively removing the bilayer hardmask from over the first region of the substrate further comprises--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20200312662 A1), hereinafter “Chang”.
Regarding claim 1, Chang discloses (see, for example, figs 13 and 14) a method of forming a semiconductor structure, the method comprising:
seating a substrate (fig. 14, element 102, para [0014]) comprising a first region (fig. 13, element 140, para [0044]) and a second region (fig. 13, element 142, para [0044]) into a reaction chamber (see, “ALD…CVD, para [0042]); and
forming a bilayer hardmask (fig. 14, element 148 comprising layers 144 and 146, paras. [0041]- [0044]) on the substrate (fig. 14, element 102, para [0014]), wherein forming the bilayer hardmask comprises:
performing one or more deposition cycles of a first cyclical deposition process (“formed by ALD”, see para [0041]-[0042]) to deposit a first hardmask layer (fig. 14, elements 144, paras. [0042]-[0043]) comprising a first metal oxide (fig. 14, element 144, para [0043]) on the substrate; and
performing one or more deposition cycles of a second cyclical deposition process (formed by ALD”, see paras. [0041]-[0042]) to deposit a second hardmask layer (fig. 14, element 146, paras. [0041]-[0042] and [0044]) comprising a second metal oxide (para [0044]) on the first hardmask layer.
Regarding claims 2: Chang discloses the method claim 1, wherein a first unit deposition cycle of the first cyclical deposition process (paras. [0041]-[0042]) comprises;
providing a first metal precursor (para [0043]) to the reaction chamber; and
providing a first oxidizer to the reaction chamber (para [0043]).
Regarding claim 3: Chang discloses method claim 2, wherein the first hardmask layer comprises aluminum oxide (para [0043]).
Regarding claim 4: Chang discloses method claim 3, wherein a second unit deposition cycle of the second cyclical deposition process (paras. [0041]-[0042]) comprises;
providing a second metal precursor to the reaction chamber (para. [0044]); and
providing a second oxidizer to the reaction chamber (para. [0044]).
Regarding claim 5: Chang discloses method claim 4, wherein the second hardmask layer comprises aluminum oxide (para [0043]) and a second different metal oxide (para [0044]).
Regarding claim 6: Chang discloses method claim 4, wherein the second hardmask layer is selected from the group consisting of hafnium oxide, zirconium oxide, and yttrium oxide (para [0044] and [0056]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 8, 10, 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20200312662 A1) in view of Wu et al. (20130168771 A1).
Regarding claim 7, Chang discloses all the limitations of claim 1.
Chang does not disclose selectively removing the bilayer hardmask from over the first region of the substrate to expose a surface of the first region of the substrate.
However, Wu teaches selectively removing the bilayer hardmask from over the first region of the substrate to expose a surface of the first region of the substrate (fig. 8, element 219, para [0022]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teaching of Wu to selectively remove the bilayer hardmask from over the first region of the substrate to expose a surface of the first region of the substrate. One would have been motivated to expose the first region of the substrate to grow a conductive feature such as III-V material using epitaxy process (Wu para [0023]).
Regarding claim 8: Modified Chang discloses all of the limitations of claim 7.
Chang does not disclose wherein selectively removing the bilayer hardmask from over the first region of the substrate further comprises, forming a patterned resist layer over the second region of the substrate and contacting an exposed region of the bilayer hardmask with a wet etchant.
However, Wu discloses wherein selectively removing the bilayer hardmask from over the first region of the substrate further comprises, forming a patterned resist layer over the second region (para [0022]) of the substrate and contacting an exposed region of the bilayer hardmask with a wet etchant (para [0022]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teaching of Wu to selectively remove the hardmask from the first region, forming a patterned resist layer over the second region, and contacting an exposed region of the bilayer hardmask with a wet etchant. One would have been motivated to expose the first region of the substrate to grow a conductive feature such as III-V material using epitaxy process (Wu: para [0023]).
Regarding claim 10, Chang in view of Wu discloses the method of claim 7. Chang and Wu do not explicitly disclose further comprising, performing a cleaning process on the exposed surface of the first region of substrate thereby forming a cleaned first region surface.
However, Wu teaches subsequently performing an epitaxial deposition process on the exposed first region (Wu, para [0023]). It is notoriously well-known in the art of semiconductor manufacturing to perform a pre-epitaxial surface cleaning on an exposed semiconductor surface prior to epitaxial growth in order to remove native oxides and contaminants.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chang and Wu to include performing a cleaning process on the exposed surface of the first region. A person of ordinary skill would have been motivated to perform such a cleaning step prior to the epitaxial deposition taught by Wu in order to remove contaminants and native oxides, thereby ensuring a high-quality, defect-free epitaxial layer with good adhesion.
Regarding claim 13: Chang discloses all of the limitations of claim 12.
Chang does not disclose further comprising, forming a semiconductor layer on the cleaned first region surface.
However, Wu discloses further comprising, forming a semiconductor layer (para [0023]) on the cleaned first region surface.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teaching of Wu to form a semiconductor layer on the cleaned first region surface. One would have been motivated to have the cleaned first region to deposit semiconductor layer with good adhesion and free of contaminants.
Regarding claim 14: Chang discloses all of the limitations of claim 13.
Chang does not disclose wherein forming the semiconductor layer comprises, depositing the semiconductor layer directly on the cleaned first region surface by an epitaxial deposition process.
However, Wu discloses wherein forming the semiconductor layer comprises, depositing the semiconductor layer directly on the cleaned first region surface by an epitaxial deposition process (para [0023]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teaching of Wu to deposit the semiconductor layer on the cleaned surface of the first region using the epitaxial process. One would have been motivated to deposit semiconductor layer on the cleaned first region surface using epitaxial process to reduce strain and defects in the epitaxial structure.
Regarding claim 15: Chang discloses all of the limitations of claim 14.
Chang does not disclose further comprising, removing any remaining portions of the bilayer hardmask from over the second region.
Wu discloses further comprising, removing any remaining portions of the bilayer hardmask from over the second region (fig. 11, para [0026]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teaching of Wu to remove any remaining portions of the bilayer hardmask from over the second region. One would have been motivated to remove the remaining portions of hardmask over the second region to avoid contamination.
Regarding claim 16, Chang discloses (see, for example, figs. 13 and 14) a method of forming a semiconductor structure, the method comprising:
seating a substrate (fig. 1, element 102, para [0014]) comprising a first region (fig. 13, element 140, para [0044]) and a second region (fig. 13, element 142, para [0044]) into a reaction chamber (see, “ALD…CVD, para [0042]);
depositing a bilayer hardmask (fig. 14, elements 144 and 146, paras. [0041]-[0044]) over the first region (144) and over the second region (146), wherein depositing the bilayer hardmask (144/146) comprises;
depositing (“formed by ALD”, see para [0042]) a first hardmask layer (144) over both the first region (fig.13, element 140) and the second region (fig. 13, element 142); and
depositing (“formed by CVD”, see para [0042]) a second hardmask layer (fig. 14, element 146) over the first hardmask layer;
Chang does not explicitly teach about a first region being NMOS region and a second region being PMOS region of a semiconductor structure;
selectively removing the bilayer hardmask over the NMOS region to expose a surface of the NMOS region;
performing a cleaning process on the exposed surface of the NMOS region thereby forming a clean NMOS surface;
depositing a semiconductor layer on the clean NMOS surface; and
removing a remaining portion of the bilayer hardmask disposed over the PMOS region.
However, Wu while disclosing a method of forming a CMOS FinFet device teaches (see, for example, fig. 8) the semiconductor structure as:
seating a substrate (fig. 2, element 210, para [0016]) comprising a first region being NMOS region (fig. 8, element 219, para [0022]) and a second region being PMOS region (fig. 8, element 221, para [0022]) into a reaction chamber (“formed by CVD”/”ALD”, see para [0021]) ;
depositing a bilayer hardmask (fig.7, element 216, para [0021] and fig. 10, element 224, para [0025]) over the NMOS region and over the PMOS region, wherein depositing the bilayer hardmask comprises;
depositing a first hardmask layer (fig.7, element 218, para [0021] and fig. 10, element 226, para [0025]) over both the NMOS region and the PMOS region; and
depositing a second hardmask layer (fig.7, element 220, para [0021] and fig. 10, element 228, para [0025]) over the first hardmask layer;
selectively removing (see, fig. 8, para [0022]) the bilayer hardmask (216) over the NMOS region (219) to expose a surface of the NMOS region (exposing a top surface of the fins 212a and 212b), see para [0022]);
performing a cleaning process on the exposed surface of the NMOS region thereby forming a clean NMOS surface;
depositing (“epitaxy process”, see para [0023]) a semiconductor layer (222) on the clean NMOS surface (surface of 212a/212b); and
removing (“CMP process applied”, fig. 9, para [0024]) a remaining portion of the bilayer hardmask (216) disposed over the PMOS region (221).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chang with the teachings of Wu by applying Chang’s bilayer hardmask to a CMOS integration scheme. A person of ordinary skill would have been motivated to designate the first and second regions of Chang as NMOS and PMOS regions, selectively remove the hardmask over the NMOS region, and perform epitaxial deposition as taught by Wu, in order to selectively process different conductivity type regions with different channel materials to obtain improved carrier mobility (Wu, paras [0061] and [0064]). Furthermore, while Wu does not explicitly detail the cleaning step, it would have been obvious to perform a pre-epitaxial surface clean on the exposed NMOS surface prior to the epitaxial growth to remove native oxides and ensure a high-quality, defect-free epitaxial layer, as such cleaning is a notoriously well-known and standard requirement in the art prior to epitaxy.
Regarding claim 17: Wu discloses all of the limitations of claim 16.
Wu does not disclose wherein the bilayer hardmask is deposited by a cyclical deposition process.
However, Chang discloses wherein the bilayer hardmask is deposited by a cyclical deposition process (para [0041]-[0042]).
It would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention, to modify Wu with the teachings of Chang to deposit the bilayer hardmask by using a cyclical deposition process. One would have been motivated to deposit the bilayer hardmask by using a cyclical deposition process which grow thin films of one atomic layer at a time with uniform thickness.
Regarding claim 18: Chang discloses all of the limitations of claim 16.
Chang does not disclose wherein the semiconductor layer is deposited by an epitaxial deposition process.
However, Wu discloses wherein the semiconductor layer is deposited by an epitaxial deposition process (para [0023]).
It would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention, to modify Chang with the teachings of Wu wherein the semiconductor layer is deposited by an epitaxial deposition process. One would have been motivated to deposit semiconductor layer using epitaxial process to reduce strain and defects in the epitaxial structure.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0312662 A1) in view of Wu et al. (US 2013/0168771 A1), and further in view of Ho et al. (US 2003/0148625 A1).
Regarding claim 9, Chang discloses all of the limitations of claim 8.
Chang does not disclose wherein the wet etchant is selected from the group consisting of hydrofluoric acid, sulfuric acid, and phosphoric acid.
However, Wu teaches hydrofluoric acid (Wu: para [0017]) as an etchant to etch the dielectric layer to expose the substrate (Wu: fig. 1, element 210).
Ho et al. (US 20030148625 A1) also discloses wherein the wet etchant is selected from the group consisting of hydrofluoric acid, sulfuric acid, and phosphoric acid (Ho: para [0032]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang with the teachings of Wu and Ho wherein the wet etchant is selected from the group consisting of hydrofluoric acid, sulfuric acid, and phosphoric acid. One would have been motivated to expose the desired layer (dielectric/hardmask) using wet etchants of unique chemical properties to remove contaminants and prepare the surface for the subsequent epitaxy process (para [0023]).
Regarding claim 19, modified Chang discloses all the limitations of claim 16.
Modified Chang does not disclose wherein selectively removing the bilayer hardmask over the NMOS region further comprises, forming a patterned resist layer over the PMOS region and contacting an exposed region of the bilayer hardmask with a wet etchant selected from the group consisting of hydrofluoric acid, sulfuric acid, and phosphoric acid.
However, Wu discloses wherein selectively removing the bilayer hardmask over the NMOS region further comprises, forming a patterned resist layer over the PMOS region and contacting an exposed region of the bilayer hardmask with a wet etchant selected from the group consisting of hydrofluoric acid (Wu: para [0017]), sulfuric acid, and phosphoric acid. Ho also teaches hydrofluoric acid, sulfuric acid, and phosphoric acid as a wet etchants ([para [0032]). (MPEP 2144.07)
It would have been obvious to a person of ordinary skill in the art at the time of the invention to further modify the method of Chang and Wu by selecting the specific wet etchants of Ho (e.g., HF, sulfuric acid, or phosphoric acid). While Wu teaches the use of HF generally, Ho explicitly teaches that these specific acids are highly effective wet etchants for removing high-k metal-oxide films (such as the metal-oxide hardmask of Chang). A person of ordinary skill would have been motivated to utilize the etchants of Ho to ensure the metal-oxide hardmask of Chang could be successfully and cleanly removed during the selective patterning steps of Wu.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0312662 A1) in view of Wu et al. (US 2013/0168771 A1), and further in view of Kao et al. (US 2011/0223755 A1).
Regarding claim 11: Chang and Wu disclose all of the limitations of claim 10.
Chang and Wu do not teach wherein the cleaning process comprises, contacting the exposed surface of the first region with a plasma generated from a gas mixture comprising a fluorine containing gas and ammonia.
However, Kao discloses wherein the cleaning process comprises, contacting the exposed surface of the first region with a plasma generated from a gas mixture (fig. 1, para [0092]- [0094]) comprising a fluorine containing gas and ammonia for the removal of silicon oxide.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, to modify Chang and Wu with the teachings of Kao to perform a cleaning process of the first region with a plasma generated from a gas mixture comprising a fluorine containing gas and ammonia. One would have been motivated to use plasma generated gas mixture comprising fluorine containing gas and ammonia to enable effective cleaning and removal of contaminants and prepare the surface for further processing.
Allowable Subject Matter
Claims 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12, the prior art of record fails to teach the cleaning process as claimed. In the claimed invention, the cleaning process removes the second hardmask layer from over the second region.
Regarding claim 20, the prior art of record fails to teach the cleaning process as claimed. In the claimed invention, the cleaning process removes the second hardmask layer from over the PMOS region whilst maintaining at least a portion of the first hardmask layer over the PMOS region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Reference in Non-Patent Documents (NPL) teaches combination of Hafnium oxide and Aluminum oxide (HfO2/Al2O3) bilayered high-k dielectric is a better choice for SiC than individual Aluminum oxide layer because of the higher value of the effective dielectric constant.
Any inquiry concerning this communication from the examiner should be directed to Berhanu G Demissie whose telephone number is (571)270-0898. The examiner can normally be reached M -F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Berhanu G. Demissie/ Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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