DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: further comprising a CMOS Bonded Array (CBA) memory tile physically and electrically coupled to the signal carrying medium, the memory tile comprising a first semiconductor tile bonded to a second semiconductor tile, wherein a bottommost volatile memory tile of the one or more memory tiles is physically and electrically coupled to the CBA memory tile.
Claim(s) 8-11 depend from claim 7 and as such are therefore objected for the same reasons.
Claim(s) 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 12 and 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim requires, in part, a high bandwidth memory. It is unknown what the present Application considers high bandwidth memory. Does it define it by the width of bits, more than 32 bits, more than 64 bits, or does it define the memory based on high speed: how fast the memory is accessible and what speed is considered high. The claim is found unbounded and indefinite. While regarding claim 4, it also requires a high bandwidth memory without first defining the physical limits of such memory; moreover, it also requires “the CBA memory tile” without first providing antecedent for such claim limitation. The claims is found indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20060267173 to Takiar et al. (“Takiar”) in view of U.S. Patent/Publication No. 8817511 to McCarthy et al. (“McCarthy”), and further in view of US 20240411709 to Dally et al. (“Dally”).
As to claim 1, Takier teaches substantially the claimed invention: A processing core, comprising: a signal-carrying medium (As found in at least FIG. 5: core 500 comprising signal-carrying medium 502; note current/voltage carrying bond wires coupling to 502); one or more volatile memory tiles electrically coupled to the signal carrying medium (As found in at least FIG. 5: memory 504-510 coupled to 502); a processor physically and electrically coupled to an uppermost volatile memory tile of the one or more volatile memory tiles (As found in at least FIG. 5: processor 512 at top of stack).
While Takier may not expressly teach that 504-510 are “volatile” memory, Dally, complementarily and relevantly, teaches in at least FIG. 1A: stack of volatile memory Die1-Die8; also see at least [0039]: DRAM.
Furthermore, while Takiar teaches 512 as being a controller, it is well-known and well-understood that processor devices are also known as controller since they have means to control operations of memory and other peripheral circuits. Case in point, McCarthy, relevantly and complementarily, in at least Column 6, lines 55-59: “some implementations may have the controller functionality handled by the host device, such as by a processor of a standard processor-based computing system.”
Takiar and McCarthy and Dally are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having stacks of devices.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Takiar as set forth in this Office action and as found in the reference with the relevant and complementary teachings of McCarthy and Dally also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: the relevant art teaches that memory, whether volatile or non-volatile can be arranged in stacks and that processors perform controlling tasks.
Therefore, it would have been obvious to combine Takiar with McCarthy and Dally to make the above modification.
As to claim 2, see rejection to at least claim 1.
As to claim 3, while Takiar teaches in at least FIG. 5 a processor 512 at top of a stack, the teachings may not expressly include wherein the one or more volatile memory tiles have a same footprint as the processor.
Yet, the teachings of Dally obviate this claim, as found in at least FIG. 1A, a processor Die 110 is presented having the same footprint as the rest of the stack. Moreover, the universe of two possibilities: the processor at top or at bottom of a stack are exhausted.
As to claim 5, Takiar teaches wherein the processor comprises one or more processing cores (As found in at least [0177]: processors may comprise one or more cores).
As to claim 6, Takiar teaches wherein the processor is one of a graphics processing unit and an artificial intelligence processor (As found in at least [0004]: processor with a graphics processing unit).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights