DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention I, Species A (Fig. 1; Claims 1-16) in the reply filed on 07/08/2026 is acknowledged.
Further during an interview with Mary Lamorta on 08/28/2026 further Election of Species A (Fig. 1, Claims 1-6, 8, 11-13 and 15-16) was made without traverce..
Claims 7, 9, 14 and 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/08/2026 and 08/28/2026.
Specification
The disclosure is objected to because of the following informalities:
[0050] Reference character 100 designates no element in any figure.’
[0052] 120 designates the first semiconductor chip not the second semiconductor chip. 123A is the first through via; the second through via is 123B.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8 and 11-13, 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the passive component includes at least one trench and a
second pad disposed on a first surface thereof and connected to the trench.
It is unclear whether the trench applies to exactly one of the plural trenches, each trench of the plurality or the plurality collectively.
For the purposes of examination, the Examiner will treat “the trench” as --the at least one trench”
Claim 1 recites two separate instances of “a first surface thereof”
“the first semiconductor chip includes a first through via that extends through at least a portion of the first semiconductor chip, and a first pad disposed on a first surface thereof”
The nearest available antecedent for “thereof” is the first through via, not the first semiconductor chip.
“the passive component includes a second pad disposed on a first surface thereof,”
Here “thereof” may refer to the trench or to the passive component.
Claim 1 is indefinite for ambiguous antecedent reference.
Claim 2 recites “the first semiconductor chip further includes a first insulating layer disposed on the first surface thereof” and “the passive component further includes a second insulating layer disposed on the first surface thereof”.
Since Claim 1 introduced two distinct “first surfaces” belonging to two distinct elements, the definite relations in Claim 2 are ambiguous as to which antecedent is involved. Same defect recurs in Claim 3 and 5.
Claim 5 recites “the first insulating layer is disposed adjacent to a side surface of the third pad as well”
It is not clear if “as well” is the limitation is additive to Claim 2 limitation (“adjacent to a side surface of the first pad,”) or substitutional. Formal claim language is required see 37 CFR § 1.75(a) (e.g. the first insulating layer is further disposed adjacent to a side surface of the third pad.)
Claim 6, 8 and 11 are rejected as being dependent on Claim 1.
Claim 12 recites “first pad disposed on a first surface thereof” (first semiconductor chip), then “, a second pad disposed on the first surface”, then “a third pad disposed on a first surface thereof” (passive component), then “a second insulating layer disposed on the first surface adjacent to a side surface of the third pad”. By the time the final “the first surface” is reached, two candidate antecedents are in play. Although the ordering on wherein clauses suggests the intendent referent. 35 USC § 112 requires reasonable certainty, suggest is not the standard.
The Examiner recommends replacing “thereof” with express element name (e.g. a first surface of the first semiconductor chip”, “a first surface of the passive component”)
Claims 13 and 15-16 are rejected as being dependent on Claim 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8, 11, 12, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0082890 A1) in view of Yu et al. (US 2022/0262778 A1).
Regarding Claim 1, Kim (Fig. 1) discloses a semiconductor package, comprising:
a substrate (160);
a first semiconductor chip (110) disposed on the substrate (160);
a second semiconductor chip (120) disposed on the first semiconductor chip (110);
a passive component (130) disposed on the first semiconductor chip (110); and
an encapsulant (150, 154) that encapsulates the second semiconductor chip (120) and the passive component (130), wherein
the first semiconductor chip (110) includes a first through via (140a) that extends through at least a portion of the first semiconductor chip (110), and a first pad (via 140a terminus) disposed on a first surface thereof and connected to the first through via (144a),
the passive component (130) includes a second pad (pad of 130 connected to 144a) disposed on a first surface thereof, and
the first pad (144a) and the second pad (via 140a termius) are bonded by contacting each other (See Fig. 1).
Kim does not explicitly disclose the passive component includes at least one trench and the first pad and the second pad are directly bonded by contacting each other
Yu (Fig. 1, 3,-6, 21-28) discloses a passive component (deep trench capacitors 49) includes at least one trench (deep trench capacitors) and a second pad (50) disposed on a first surface thereof and connected to the trench, and a first pad (40a) and the second pad (50) are directly bonded by contacting each other (“The bonding may be achieved through hybrid bonding. For example, bond pads 50 are bonded to bond pads 40A through metal-to-metal direct bonding.“) [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu such that the passive component includes at least one trench and a second pad disposed on a first surface thereof and connected to the trench, and the first pad and the second pad are directly bonded by contacting each other in order to form high-density capacitors in a capacitor die have short paths to the devices in the device die and minimize package thickness [0011, 0066]
Regarding Claim 2, Kim in view of Yu discloses the semiconductor package of claim 1, wherein
Kim in view of Yu as previously combined does not explicitly disclose the first semiconductor chip further includes a first insulating layer disposed on the first surface thereof and adjacent to a side surface of the first pad, the passive component further includes a second insulating layer disposed on the first surface thereof and adjacent to a side surface of the second pad, and the first insulating layer and the second insulating layer are directly bonded by contacting each other.
However, Yu discloses a first semiconductor chip (22,30/22,75) further includes a first insulating layer (38/75) disposed on a first surface thereof and adjacent to a side surface of a first pad (40a) (“The top surface dielectric layer 38 and bond pads 40 are planarized so that their top surfaces are coplanar,” [0022]), the passive component (42) further includes a second insulating layer (52) disposed on the first surface thereof and adjacent to a side surface of the second pad (50) (“Capacitor die 42 includes bond pads 50 and dielectric layer 52 at the illustrated top surface of capacitor die 42” [0025]), and
the first insulating layer and the second insulating layer are directly bonded by contacting each other. (“dielectric layers 52 are bonded to surface dielectric layer 38 through fusion bonding, for example, with Si-O-Si bonds generated.” [0026])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu such that the first semiconductor chip further includes a first insulating layer disposed on the first surface thereof and adjacent to a side surface of the first pad, the passive component further includes a second insulating layer disposed on the first surface thereof and adjacent to a side surface of the second pad, and the first insulating layer and the second insulating layer are directly bonded by contacting each other in order to use direct bond (copper-to-copper and dielectric fusion bonding) technique which shortens paths to the devices in the device die and minimize package thickness [0011, 0066].
Regarding Claim 3, Kim in view of Yu discloses the semiconductor package of claim 2, wherein
the first semiconductor chip (110) further includes a third pad (TSV’s terminus at the first surface) disposed on the first surface thereof that is spaced apart from the first pad (140a), and the second semiconductor chip (120) includes a fourth pad (chip 120 contacted via to second micro-bum 144b) disposed on a first surface thereof and connected to the third pad. (See Fig. 2)
Regarding Claim 8, Kim in view of Yu discloses the semiconductor package of claim 1, wherein
the first semiconductor chip (110) further includes a second through via (140b) that extends through at least a portion of the first semiconductor chip (110) and electrically connects the second semiconductor chip (120) to the first semiconductor chip (110).
Regarding Claim 11, Kim in view of Yu discloses the semiconductor package of claim 1, wherein
the passive component is an integrated stacked capacitor (ISC). (Yu, (Fig. 2)
Regarding Claim 12, Kim discloses a semiconductor package, comprising:
a substrate (160);
a first semiconductor chip (110) disposed on the substrate (160);
a second semiconductor chip (120) disposed on the first semiconductor chip (110);
a passive component (130) disposed on the first semiconductor chip (110); and
an encapsulant (150, 154) that encapsulates the second semiconductor chip (120) and the passive component (130), wherein
the first semiconductor chip (110) includes a first through via (140a) that extends through at least a portion of the first semiconductor chip (110) and electrically connects the passive component (130) and the first semiconductor chip (110), a first pad (144a) disposed on a first surface thereof and connected to the first through via (140a),
a second through via (140b) that extends through at least a portion of the first semiconductor chip (110) and electrically connects the second semiconductor chip (120) to the first semiconductor chip (110), a second pad (via 140b terminus) disposed on the first surface and connected to the second through via (140b), and a first insulating layer (142) disposed on the first surface adjacent to a side surface of each of the first pad and the second pad (Fig. 2).
Kim does not explicitly disclose the passive component includes a third pad disposed on a first surface thereof and a second insulating layer disposed on the first surface adjacent to a side surface of the third pad, and the first pad and the third pad are directly bonded by contacting each other.
Kim (Fig. 1, 3,-6, 21-28) discloses a passive component (42) includes a third pad (50) disposed on a first surface thereof and a second insulating layer (52, see separate insulating layers 52 for multiple devices) disposed on the first surface adjacent to a side surface of the third pad (50), and a first pad (40a) and the third pad (50) are directly bonded by contacting each other. (“The bonding may be achieved through hybrid bonding. For example, bond pads 50 are bonded to bond pads 40A through metal-to-metal direct bonding. “) [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu to use laterally spaced insulating layer interfaces such that the second insulating layer and the third insulating layer are spaced apart and that the passive component includes a third pad disposed on a first surface thereof and a second insulating layer disposed on the first surface adjacent to a side surface of the third pad, and the first pad and the third pad are directly bonded by contacting each other in order to form high-density capacitors in a capacitor die have short paths to the devices in the device die and minimize package thickness [0011, 0066].
Regarding Claim 15, Kim in view of Yu discloses the semiconductor package of claim 12, wherein
the first pad and the second pad are disposed at the same level. [0025 Yu]
Regarding Claim 16, Kim in view of Yu discloses the semiconductor package of claim 12, wherein
the first insulating layer and the second insulating layer are directly bonded by contacting each other. [0026 Yu]
Claim(s) 4-6, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0082890 A1) in view of Yu et al. (US 2022/0262778 A1) and further in view Hu et al. (US 2019/0148342 A1).
Regarding Claim 4, Kim in view of Yu discloses the semiconductor package of claim 3.
Kim in view of Yu as previously combined does not explicitly disclose the third pad and the fourth pad are directly bonded by contacting each other.
However, Yu discloses copper-to-copper direct bonding technique, applied by combination at the cache-chip interface.
Hu (Fig. 2) discloses a third pad (46A/46) and a fourth pad (146) are directly bonded by contacting each other. (“bond pads 146 are bonded to bond pads 46A and 46C through metal-to-metal direct bonding.”) [0031]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu and Hu such that the third pad and the fourth pad are directly bonded by contacting each other in order to use direct bond (copper-to-copper) technique which shortens paths to the devices in the device die and minimize package thickness [0031].
Regarding Claim 5, Kim in view of Yu and Hu discloses the semiconductor package of claim 4, wherein
the first insulating layer (38/75 Yu) (42 Hu) is disposed adjacent to a side surface of the third pad (46A Hu) as well, the second semiconductor chip (112 Hu) further includes a third insulating layer (142) disposed on the first surface thereof and adjacent to a side surface of the fourth pad (146 Hu), and the first insulating layer (38/42) and the third insulating layer (146) are directly bonded by contacting each other. (“dielectric layers 52 are bonded to surface dielectric layer 38 through fusion bonding, for example, with Si-O-Si bonds generated.” [0026] Yu) (“, dielectric layers 142 are bonded to surface dielectric layer 42 through dielectric-to-dielectric bonding, which may be fusion bonding, for example, with Si—O—Si bonds generated” [0031] Hu)
Regarding Claim 6, Kim in view of Yu and Hu discloses the semiconductor package of claim 5, wherein
Kim in view of Yu and Hu does not explicitly disclose that the second insulating layer and the third insulating layer are spaced apart from each other.
However, Kim discloses that the cache memory chip 120 and the passive device module 130 may be disposed side-by-side to be adjacent to each other in a horizontal direction (X-direction or Y-direction) on the application processor 110 [0032].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu and Hu such that topology of Kim is applied to Yu dielectric bond structure of laterally separated sites resulting in laterally spaced insulating layer interfaces such that the second insulating layer and the third insulating layer are spaced apart from each other in order to in order to use direct bond (copper-to-copper) technique which shortens paths to the devices in the device die and minimize package thickness [0031].
Regarding Claim 13, Kim in view of Yu discloses the semiconductor package of claim 12, wherein
Kim in view of Yu as previously combined does not explicitly disclose the second semiconductor chip includes a fourth pad disposed on a first surface thereof, and the second pad and the fourth pad are directly bonded by contacting each other.
However, Yu discloses copper-to-copper direct bonding technique, applied by combination at the cache-chip interface.
Hu (Fig. 2) discloses a second semiconductor chip (112) includes a fourth pad (146) disposed on a first surface thereof, and a second pad (46A/46) and the fourth pad (146) are directly bonded by contacting each other. (“bond pads 146 are bonded to bond pads 46A and 46C through metal-to-metal direct bonding.”) [0031]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Yu and Hu such that the second semiconductor chip includes a fourth pad disposed on a first surface thereof, and the second pad and the fourth pad are directly bonded by contacting each other in order to use direct bond (copper-to-copper) technique which shortens paths to the devices in the device die and minimize package thickness [0031].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huanget al. (US 2021/0296283 A1) discloses hybrid/direct bonding of passive components.
An et al. (US 2022/0045038 A1) discloses semiconductor chip and passive component arrangement and bonding.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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