DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-18, drawn to a semiconductor (3D EEPROM) in the reply filed on 6/17/2026 is acknowledged.
Claims 19-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention [a method of manufacturing a semiconductor device (3D integrated device)], there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/17/2026.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-13, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11437318 B2 Nguyen et al hereafter “Nguyen”.
Claim 1 Nguyen teaches in fig 5A-5C a semiconductor device (304) comprising:
a peripheral circuit (conductive structures 353 and/or conductive tier 351 of Nguyen [best illustrated fig. 5B and/or 5C] structural and/or compositionally matches the peripheral circuits 10(PC) as disclosed and/or illustrated fig. 1B/C within the instant application, thus 353 of Nguyen qualifies as “peripheral circuits” under MPEP 2112.01);
a gate structure (336 comprising 334 and 332, met under MPEP 2112.01 the structure matches 11 and 12 of fig. 1B/C of the instant application) disposed on the peripheral circuit [sufficiently illustrated], the gate structure including stacked gate lines (334);
a first recess staircase structure (left 338) disposed within the gate structure; a second recess staircase (right 338) structure disposed within the gate structure adjacent to the first recess staircase structure in a first direction (X);
a first gap-fill insulating layer (343) including a first line portion (343 in and/or contacting left 338, see annotation below) formed within the first recess staircase structure,
a second line portion (343 in and/or contacting right 338, see annotation below) formed within the second recess staircase structure, and a bridge portion (343 between left and right 338) disposed between the first line portion and the second line portion connecting the first line portion and the second line portion to each other [sufficiently illustrated, see annotation below]; and
peripheral contact plugs (350) extending into the gate structure through the bridge portion of the first gap-fill insulating layer and connected to the peripheral circuit [at least a portion of 350 are sufficiently illustrated as such, see annotation below].
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Annotated fig. 5B; highlighting the Bridge portion and line portions in a first cross-section of the device of fig. 5A
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Annotated fig. 5C; highlighting the Bridge portion and line portions in a second cross-section of the device of fig. 5A
Claim 5 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the first gap-fill insulating layer has a ladder shape [met under broadest reasonable interpretation the gap-fill insulating layer has the projected shape of a step and/or stair ladder as it is conformal to the recess staircase structures in the Z-X plane].
Claim 6 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the first line portion and the second line portion extend in a second direction (Y) intersecting the first direction, and the bridge portion extends in the first direction [sufficiently illustrated fig. 5B and 5C in view of fig. 5A].
Claim 7 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the first line portion and the second line portion have bottom surfaces having a staircase shape [sufficiently illustrated].
Claim 8 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the first line portion and the second line portion extend into the gate structure, and the bridge portion is located on the gate structure [sufficiently illustrated].
Claim 9 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, further comprising:
a first channel structure (left 356) extending through the gate structure; and
a second channel structure (right 356) extending through the gate structure.
[met under MPEP 2112.01 and disclosed with sufficient specificity “Each of the pillar structures 156 may include a semiconductive pillar (e.g., a polycrystalline silicon pillar, a silicon-germanium pillar)” and “Intersections of the pillar structures 156 and the conductive structures 134 (FIGS. 3B and 3C) of the tiers 136 (FIGS. 3B and 3C) of the block 114 may define vertically extending strings of memory cells 158”column 15 lines 50-55 wherein 356, 334, 336, and 314 are illustrated/disclosed as being substantially identical].
Claim 10 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 9, wherein the first recess staircase structure and the second recess staircase structure are located between the first channel structure and the second channel structure [sufficiently illustrated].
Claim 11 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 9, further comprising:
a third recess staircase structure located between the first channel structure and the first recess staircase structure; and a fourth recess staircase structure located between the second channel structure and the second recess staircase structure. [Sufficiently illustrated, see annotated below].
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Nguyen Annotated fig. 5A: highlighting a plurality of recess staircase structures in view of Fig. 5b and Fig. 5C
Claim 12 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 11, further comprising: a third gap-fill insulating layer formed within the third recess staircase structure; and
a fourth gap-fill insulating layer formed within the fourth recess staircase structure.
[sufficiently illustrated the structure of the third and fourth recess staircase structure are substantially identical to that of the first and third, including the gap-fill insulating layers].
Claim 13 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, further comprising:
first cell contact plugs (348 and/or 350 of left 338) extending through the first line portion of the first gap-fill insulating layer and connected to the first recess staircase structure [sufficiently illustrated]; and
second cell contact plugs (348 and/or 350 of right 338) extending through the second line portion of the first gap-fill insulating layer and connected to the second recess staircase structure [sufficiently illustrated].
Claim 15 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the peripheral contact plugs are spaced apart from an edge of the bridge portion [met under broadest reasonable interpretation the contact plugs appear to spaced in the center of the bridge portion and not on the edges, sufficiently illustrated].
Claim(s) 14 is/are rejected under 35 U.S.C. 102 as being anticipated by Nguyen and/or in the alternative 35 U.S.C. 103 as being unpatentable over Nguyen as applied to the claims above.
Claim 14 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1, wherein the peripheral contact plugs include:
a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and a second peripheral contact plug connected to a junction of the transistor. [not explicitly illustrated but disclosed with sufficient specificity, “The conductively filled vias 150 may be coupled to a group of conductive structures 153 of the conductive tier 151. The conductive structures 153 of the group may be coupled to local contact structures 130 (FIG. 2) coupled to some of the string driver transistors 116 (FIG. 2) of the string driver circuitry 112 (FIG. 2) within the base structure 102 (FIGS. 1 and 2)” Column 13 lines 15-25 wherein 350 and 353 are substantially identical to 150 and 153]
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nguyen such that “a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and a second peripheral contact plug connected to a junction of the transistor.” For the benefit of electrically powering and addressing the transistors within the base structure from the top side of the device (front end of line layers).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen as applied to the claims above, and further in view of US 20110115010 A1 Shim et al hereafter “Shim”.
Claim 2 Nguyen teaches in fig. 5A-C as shown above the semiconductor device of claim 1,
Nguyen does not teach further comprising a second gap-fill insulating layer formed on the gate structure and surrounded by the first line portion, the second line portion, and the bridge portion.
Shim teaches a semiconductor device wherein a first gap-fill insulating layer (124a fig. 11A) including a first line portion (124a of 80 fig. 11A) formed within a first recess staircase structure (80 fig. 11A), and a second line portion (124a of 80 fig. 11A, in view of the embodiment of fig. 4D) formed within a second recess staircase structure (80 fig. 11A, in view of the embodiment of fig. 4D);
A second gap-fill insulating layer (top most 108a fig. 6B) formed on the gate structure and surrounded by the first line portion, the second line portion [met in view of the embodiment of fig. 4D].
Further Shim teaches an alternative embodiment of the device a semiconductor device wherein a first gap-fill insulating layer (125 fig. 6B) including a first line portion (125 of 80 fig. 6B) formed within a first recess staircase structure (80 fig. 6B), and a second line portion (125 of 80 fig. 6B, in view of the embodiment of fig. 4D) formed within a second recess staircase structure (80 fig. 6B, in view of the embodiment of fig. 4D);
a portion bridge portion of the first gap-fill insulating layer (125 of 85 fig. 6B) formed on the gate structure and surrounded by the first line portion, the second line portion [met in view of the embodiment of fig. 4D].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Nguyen in view of the device of Shim such that “a second gap-fill insulating layer formed on the gate structure and surrounded by the first line portion, the second line portion”.
The reason to make this combination is to enable “a three-dimensional semiconductor memory device having good reliability and capable of operating in high speed” [Paragraph 0162 Shim].
In addition, combining and/or substituting equivalents known for the same purpose is prima facie type obviousness [2144.06].
Further it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device of Nguyen in view of Shin wherein sections comprising the “bridge portion” alternate with sections comprising the “second gap fill structure” such that the “second gap-fill insulating layer formed surrounded by the bridge portion”.
The reason to make this modification is rearrangements of parts is prima facie type obviousness [see MPEP VI C.]
In addition to combining and/or substituting equivalents known for the same purpose is prima facie type obviousness [2144.06].
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Shim as applied to the claims above, and further in view of US 20230032177 A1 Jain hereafter “Jain”.
Claim 3 Nguyen in view of Shim teaches in fig. 5A-C as shown above the semiconductor device of claim 2.
Nguyen in view of Shim does not teach the second gap-fill insulating layer includes a void, the void being spaced apart from the peripheral contact plugs.
Jain teaches devices comprising similar staircase structures (3020 fig. 30) and that air gaps are a known alternative to low-k dielectric materials in the spaces between adjacent bitlines and/or conductive layers. [Sufficiently disclosed “the spaces between adjacent first bitlines 16 may include an air gap (e.g., a void) rather than the low-k dielectric material 18. The air gap may be empty of a solid material and/or liquid material. However, the air gap may contain a gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or a combination thereof)”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nguyen in view of Shim and in further view of Jain such that “the second gap-fill insulating layer includes a void, the void being spaced apart from the peripheral contact plugs”.
The benefit of this modification is to provide dielectric isolation between adjacent conductive structures.
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP2144.06]. In this case it is known dielectric isolation structures for the purpose of providing insulation to adjacent conductive structures.
Claim 4 Nguyen in view of Shim and Jain teaches in fig. 5A-C as shown above the semiconductor device of claim 3, wherein the void extends along an edge of the first gap-fill insulating layer [met in view of the modification of Jain as shown above as the second gap fill insulating layer extends along an edge of the first gap-fill insulating layer in view of the modification of Shim].
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in as applied to the claims above, and in further view of Jain.
Claim 16 Nguyen teaches in fig. 5A-C a semiconductor device (304) comprising: a peripheral circuit (351); a gate structure [336 comprising 334 and 332, met under MPEP 2112.01, structurally and/or material matches 11 and 12 of the gate structure fig. 1B and 1C as illustrated in the instant application] disposed on the peripheral circuit and including stacked gate lines (334); a first recess staircase structure (left 338) disposed within the gate structure; a second recess staircase structure (right 338) disposed within the gate structure; a first gap-fill (343 in and/or contacting left 338) insulating layer including a first line portion formed within the first recess staircase structure, a second line portion (343 in and/or contacting right 338) formed within the second recess staircase structure, and bridge portions (343 in-between left and right 338) connecting the first line portion and the second line portion to each other; and
A portion of the first gap-fill insulating layer located between the bridge portions and between the first line portion and the second line portion [sufficiently illustrated]
Nguyen does not teach a second gap-fill insulating layer located between the bridge portions and between the first line portion and the second line portion, wherein the second gap-fill insulating layer includes a void extending along an edge of the first gap-fill insulating layer.
Jain teaches devices comprising similar staircase structures (3020 fig. 30) and that air gaps are a known alternative to low-k dielectric materials in the spaces between adjacent bitlines and/or conductive layers. [Sufficiently disclosed “the spaces between adjacent first bitlines 16 may include an air gap (e.g., a void) rather than the low-k dielectric material 18. The air gap may be empty of a solid material and/or liquid material. However, the air gap may contain a gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or a combination thereof)”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nguyen in further view of Jain such that “a second gap-fill insulating layer located between the bridge portions and between the first line portion and the second line portion, wherein the second gap-fill insulating layer includes a void extending along an edge of the first gap-fill insulating layer”.
The benefit of this modification is to provide dielectric isolation between adjacent conductive structures.
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP2144.06]. In this case it is known dielectric isolation structures for the purpose of providing insulation to adjacent conductive structures.
Claim 17 Nguyen fig. 5A-C in view of Jain teaches as shown above the semiconductor device of claim 16, further comprising peripheral contact plugs (350) extending into the gate structure through the bridge portions and connected to the peripheral circuit [met under broadest reasonable interpretation at least a portion of 350 extends into the gate structure through the bridge portion].
Claim 18 Nguyen fig. 5A-C in of Jain teaches as shown above the semiconductor device of claim 17,
wherein the peripheral contact plugs include:
a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and a second peripheral contact plug connected to a junction of the transistor. [not illustrated but disclosed with sufficient specificity, “The conductively filled vias 150 may be coupled to a group of conductive structures 153 of the conductive tier 151. The conductive structures 153 of the group may be coupled to local contact structures 130 (FIG. 2) coupled to some of the string driver transistors 116 (FIG. 2) of the string driver circuitry 112 (FIG. 2) within the base structure 102 (FIGS. 1 and 2)” Column 13 lines 15-25 wherein 350 and 353 are substantially identical to 150 and 153]
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nguyen such that “a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and a second peripheral contact plug connected to a junction of the transistor.” For the benefit of electrically powering and addressing the transistors within the base structure from the top side of the device (front end of line layers).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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