DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 20210375722.
Regarding claim 1, Kim discloses a semiconductor device, comprising:
a substrate having a first surface and a second surface opposing each other (paragraph [0023] describes substrate 101, comprising active region 102, figure 1 and figure 2, having a first and second surface);
a fin-type active pattern on the first surface of the substrate and extending in a first direction (fin pattern structures are elements 105 on the first surface of substrate 101 extending in the x-direction as shown in figures 1 and 2 [0025]) ;
a gate structure crossing the fin-type active pattern and extending in a second direction, intersecting the first direction (paragraphs [0027-0028] describes gate structure GS, comprising gate spacers 141, gate dielectric layer 142, and gate electrode 145 and extending in a second direction, as shown in figure 1);
a source/drain region on the fin-type active pattern at a side of the gate structure (paragraph [0026] discloses the source/drain regions 110 located on opposite sides of the gate structure GS, shown in figure 2) ;
an interlayer insulating unit on the substrate and covering the source/drain region (an interlayer insulating unit comprises insulating elements 162 and 165 - paragraph [0042] describes the interlayer insulating layer 165 and [0030] describes insulating element 162, covering the source/drain region 110, figure 2);
a contact structure penetrating through a portion of the interlayer insulating unit and connected to the source/drain region (paragraph [0047] discloses a contact structure 180, which penetrates through interlayer insulating layer 165 and is connected to the source/drain region 110 as shown in figure 2);
a buried conductive structure extending in the interlayer insulating unit in a direction perpendicular to the first surface of the substrate, the buried conductive structure being electrically connected to the contact structure (paragraph [0033] discloses a buried conductive line 120, which extends in the interlayer insulating layer 165 in a direction perpendicular to the first surface of the substrate 101, as shown in figures 2 and 3)
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a conductive through structure extending from the second surface of the substrate toward the first surface of the substrate and contacting the buried conductive structure (paragraph [0035] discloses the conductive through-structure 250, extending from the second surface of the substrate, which is the upper surface of the substrate 101/102 shown in figure 2, toward the lower first surface of substrate 101/102, contacting the buried conductive structure, the conductive through structure having a first width at a level adjacent to the first surface, wider than a second width at a level adjacent to the second surface (see annotated figure 7, which differs only in the position of a component not impacting the limitations of this claim as described in paragraph [0086], and a contact portion (figure 3, CT, [0034]), in which the buried conductive structure and the conductive through structure are in contact with each other, having a continuous side surface (paragraph [0035] describes the contact region CT in which the buried conductive structure 120 is in contact with conductive through structure 255 and the line of contact has a continuous side surface 120S);
and a power transmission line on the second surface of the substrate and connected to the conductive through structure (paragraphs [0052-0053] disclose that wiring portion ML2, located on the second surface through the layer 101/102, is a power transmission line connected to the conductive through structure 250) .
Regarding claim 2, Kim discloses the semiconductor device as claimed in claim 1, wherein the conductive through structure has a convex or concave upper surface (figure 3 shows that the surface of 255 has a convex shape).
Regarding claim 3, Kim discloses the semiconductor device as claimed in claim 1,wherein the conductive through structure has a width that gradually narrows as it approaches the second surface of the substrate (annotated figure 7 above in the rejection of claim 1 shows that the width of conductive structure 255 narrows as it approaches the second (upper) surface of the substrate 101/102).
Regarding claim 4, Kim discloses the semiconductor device as claimed in claim 1,wherein the buried conductive structure and the conductive through structure have continuous side surfaces (figure 2 shows that the buried conductive structure and the conductive through structure each have continuous side surfaces).
Regarding claim 5, Kim discloses the semiconductor device as claimed in claim 1, wherein:
the conductive through structure penetrates through the substrate and extends into the interlayer insulating unit (conductive through structure 250 penetrates through substrate layer 101/102 and extends into the interlayer insulating unit element 162a/165, figure 2),
and the contact portion is on the first surface of the substrate (see figure 2, where the contact portion CT is on the first surface of the substrate 101/102).
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Regarding claim 6, Kim discloses the semiconductor device as claimed in claim 5, wherein a side surface of the conductive through structure has a step portion on the first surface of the substrate (annotated figure 3 shows the step on the inside side surface of 250, which is located on the first surface of the substrate).
Regarding claim 8, Kim discloses the semiconductor device as claimed in claim 1, wherein: the buried conductive structure extends into the substrate, and the contact portion is in the substrate (figure 3 shows that the buried contact structure 120 extends into the substrate 101/102 and the contact portion CT is in the substrate 101/102).
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Regarding claim 9, Kim discloses the semiconductor device as claimed in claim 8, wherein a side surface of the buried conductive structure has a step portion on the first surface of the substrate (see annotated figure 3).
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Regarding claim 11, Kim discloses the semiconductor device as claimed in claim 1, wherein: an upper surface of the conductive through structure has a convex or concave portion, and the convex or concave portion of the conductive through structure horizontally overlaps the first surface of the substrate (annotated figure 2 below shows the upper structure of the conductive through structure has a concave surface and that the concave portion horizontally overlaps the first surface of the substrate 101/102).
Regarding claim 12, Kim discloses the semiconductor device as claimed in
claim 1, wherein the contact structure has an extension portion extending in the second direction and connected to an upper surface of the buried conductive structure (figure 1 shows that contact structure 180 has a portion extending in the y-direction, connected to the buried conductive structure 250, as illustrated).
Regarding claim 14, Kim discloses the semiconductor device as claimed in claim 1, further comprising a second wiring structure on the second surface of the substrate and having a second wiring layer connected to the power transmission line (paragraph [0052-0053] describe second wiring structure ML2 in figure 2, on the second upper surface of substrate layer 101/102, having a second wiring layer M2 [0055] connected to the power lines [0054]).
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Regarding claim 15, Kim discloses the semiconductor device as claimed in claim 1, further comprising semiconductor patterns spaced apart from each other in a direction perpendicular to the first surface of the substrate on the fin-type active pattern ((paragraph [0025] discloses that the semiconductor device comprises semiconductor patterns on the plurality of active fin structures 105 protruding upward perpendicular to the first surface of the substrate 101/102 e.g., in the z- direction), the gate structure including a gate electrode surrounding each of the semiconductor patterns and extending in the second direction (the gate structure GS including a gate electrode 145, extending in the second direction , the y-direction, and overlapping on both sides, and thus surrounding the active patterns, is described in paragraph [0027-0028] and illustrated in figures 1 and 2), and a gate insulating film (141) between each of the semiconductor patterns (110) and the gate electrode (145) (as shown in the annotated figure 100).
Regarding claim 16, Kim discloses a semiconductor device, comprising:
a substrate having a first surface and a second surface opposing each other (paragraph [0023] describes substrate 101, comprising active region 102, figure 1 and figure 2, having a first and second surface);
a fin-type active pattern on the first surface of the substrate and extending in a first direction (fin pattern structures are elements 105 on the first surface of substrate 101 extending in the x-direction as shown in figures 1 and 2 [0025]);
a gate structure crossing the fin-type active pattern and extending in a second direction, intersecting the first direction (paragraphs [0027-0028] describes gate structure GS, comprising gate spacers 141, gate dielectric layer 142, and gate electrode 145 and extending in a second direction, as shown in figure 1);
a source/drain region on the fin-type active pattern at a side of the gate structure (paragraph [0026] discloses the source/drain regions 110 located on opposite sides of the gate structure GS, shown in figure 2);
an interlayer insulating unit on the substrate and covering the source/drain region; a contact structure penetrating through a portion of the interlayer insulating unit and connected to the source/drain region (an interlayer insulating unit comprises insulating elements 162 and 165 - paragraph [0042] describes the interlayer insulating layer 165 and [0030] describes insulating element 162, covering the source/drain region 110, figure 2);
a buried conductive structure extending in the interlayer insulating unit in a direction perpendicular to the first surface of the substrate, the buried conductive structure being electrically connected to the contact structure (paragraph [0033] discloses a buried conductive line 120, which extends in the interlayer insulating layer 165 in a direction perpendicular to the first surface of the substrate 101, as shown in figures 2 and 3);
a conductive through structure penetrating through the substrate and extending to the interlayer insulating unit to have a contact with the buried conductive structure (paragraph [0035] discloses the conductive through-structure 250, extending from the second surface of the substrate, which is the upper surface of the substrate 101/102 shown in figure 2, toward the lower first surface of substrate 101/102, contacting the buried conductive structure),
an upper surface of the conductive through structure in contact with the buried conductive structure being a convex surface (figure 3 shows that the upper surface of the conductive through structure 250 in contact with the buried conductive structure 120 is a convex surface), and
the conductive through structure including a portion extending to the interlayer insulating unit and having a side surface continuous with a side surface of the buried conductive structure (figure 2 shows that the conductive through structure 250 extends to the interlayer insulating unit 162/165 and has a side continuous with a side surface of 250, as they are in direct physical contact);
and a power transmission line on the second surface of the substrate and connected to the conductive through structure (paragraphs [0052-0053] disclose that wiring portion ML2, located on the second surface through the layer 101/102, is a power transmission line connected to the conductive through structure 250).
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Regarding claim 17, Kim discloses the semiconductor device as claimed in claim 16, wherein the conductive through structure has a continuous side surface, a width of the conductive through structure gradually narrowing as it approaches the second surface of the substrate (see annotated figure 7. where the conductive through structure has a continuous side surface with no breaks and the width of the conductive through structure gradually narrows as it approaches the second surface of the substrate – the upper surface of 101/102).
Regarding claim 18, Kim discloses the semiconductor device as claimed in claim 16, wherein a side surface of the conductive through structure has a step portion on the first surface of the substrate (shown in annotated figure 3).
Regarding claim 19, Kim discloses a semiconductor device, comprising:
a substrate having a first surface and a second surface opposing each other (paragraph [0023] describes substrate 101, comprising active region 102, figure 1 and figure 2, having a first and second surface);
a fin-type active pattern on the first surface of the substrate and extending in a first direction (fin pattern structures are elements 105 on the first surface of substrate 101 extending in the x-direction as shown in figures 1 and 2 [0025]);
a gate structure crossing the fin-type active pattern and extending in a second direction, intersecting the first direction (paragraphs [0027-0028] describes gate structure GS, comprising gate spacers 141, gate dielectric layer 142, and gate electrode 145 and extending in a second direction, as shown in figure 1);
a source/drain region on the fin-type active pattern at a side of the gate structure (paragraph [0026] discloses the source/drain regions 110 located on opposite sides of the gate structure GS, shown in figure 2);
an interlayer insulating unit on the substrate and covering the source/drain region;
a contact structure penetrating through the interlayer insulating unit and connected to the source/drain region (an interlayer insulating unit comprises insulating elements 162 and 165 - paragraph [0042] describes the interlayer insulating layer 165 and [0030] describes insulating element 162, covering the source/drain region 110, figure 2);
a buried conductive structure electrically connected to the contact structure and extending into the substrate from the interlayer insulating unit (paragraph [0033] discloses a buried conductive line 120, which extends in the interlayer insulating layer 165 in a direction perpendicular to the first surface of the substrate 101, as shown in figures 2 and 3);
a conductive through structure extending from the second surface of the substrate and contacting the buried conductive structure (paragraph [0035] discloses the conductive through-structure 250, extending from the second surface of the substrate, which is the upper surface of the substrate 101/102 shown in figure 2, toward the lower first surface of substrate 101/102, contacting the buried conductive structure),
an upper surface of the conductive through structure in contact with the buried conductive structure being a non-flat surface (figure 3 shows that the upper surface of 250 in contact with 120 is not flat), and the conductive through structure having a side surface continuous with a side surface of a portion of the buried conductive structure in the substrate (figure 3 shows that 250 has a side continuous with a side surface of 120, as they are in direct physical contact);
and a power transmission line on the second surface of the substrate and connected to the conductive through structure (paragraphs [0052-0053] disclose that wiring portion ML2, located on the second surface through the layer 101/102, is a power transmission line connected to the conductive through structure 250).
Regarding claim 20, Kim discloses the semiconductor device as claimed in claim 19, wherein:
the conductive through structure and the portion of the buried conductive structure in the substrate have a width that gradually decreases as it approaches the second surface of the substrate (see annotated figure 7. where the conductive through structure has a continuous side surface with no breaks and the width of the conductive through structure gradually narrows as it approaches the second surface of the substrate – the upper surface of 101/102)., and
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a side surface of the buried conductive structure has a step portion on the first surface of the substrate (see annotated figure 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cho et al. US 20220399251.
Regarding claim 7, Kim discloses the semiconductor device as claimed in claim 5, wherein:
the buried conductive structure includes a first contact plug (figure 3 shows that the buried conductive structure 120 includes contact plug 120 and
the conductive through structure includes a second contact plug (figure 2, 255), a second insulating liner surrounding a side surface of the second contact plug (figure 2, shows insulating liner 251 surrounding the side surface of 255 [0035]).
Kim lacks a first conductive barrier surrounding a side surface and a lower surface of the first contact plug and a second conductive barrier between the second contact plug and the second insulating liner and extending to an upper surface of the second contact plug.
However, Cho discloses a similar semiconductor device including through electrodes where a first conductive barrier surrounds a side surface and a lower surface of the first contact plug of the buried conductive structure (figure 4B shows a first conductive barrier 118a surrounding the side and lower surface of the buried conductive structure plug 118b [0090]), and a second conductive barrier (figure 4B, 169a [0092-0093]) between the second contact plug (169b) and the second insulating liner (167) and extending to an upper surface of the second contact plug (figure 4B).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to add the liners of Cho to the conductive plugs as disclosed by Kim to prevent diffusion from the plug into surrounding dielectric material and improve adhesion, thereby enhancing the electrical and thermal performance.
Regarding claim 10, Kim discloses the semiconductor device as claimed in claim 8, wherein:
the buried conductive structure includes a first contact plug (figure 3 shows that the buried conductive structure 120 includes contact plug 120 and
the conductive through structure includes a second contact plug (figure 2, 255), a second insulating liner surrounding a side surface of the second contact plug (figure 2, shows insulating liner 251 surrounding the side surface of 255 [0035]).
Kim lacks a first conductive barrier surrounding a side surface and a lower surface of the first contact plug and a second conductive barrier between the second contact plug and the second insulating liner and extending to an upper surface of the second contact plug.
However, Cho discloses a similar semiconductor device including through electrodes where a first conductive barrier surrounds a side surface and a lower surface of the first contact plug of the buried conductive structure (figure 4B shows a first conductive barrier 118a surrounding the side and lower surface of the buried conductive structure plug 118b [0090]), and a second conductive barrier (figure 4B, 169a [0092-0093]) between the second contact plug (169b) and the second insulating liner (167) and extending to an upper surface of the second contact plug (figure 4B).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to add the liners of Cho to the conductive plugs as disclosed by Kim to prevent diffusion from the plug into surrounding dielectric material and improve adhesion, thereby enhancing the electrical and thermal performance.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, the prior art does not teach or render obvious the semiconductor device as claimed in claim 1, further comprising a first wiring structure on the interlayer insulating unit and having a first wiring layer connected to the contact structure, an upper surface of the buried conductive structure being connected to the first wiring layer and being connected to the contact structure through the first wiring layer in combination as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Wang et al. US 20210343639 which discloses a similar integrated circuit structure including GAA transistors and a backside rail and Oh et al. US 20220139900, which discloses a similar circuit with back-side power delivery and through vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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