Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of claims 1-10 in the “Response to Restriction Requirement” filed on 07/06/2026 is acknowledged and entered by the Examiner.
This office action consider claims 1-20 pending for prosecution, wherein claims 11-20 are withdrawn from further consideration, and claims 1-10 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 20150364538 A1; hereinafter Wang).
Regarding claim 1, Wang teaches a metal-insulator-metal (MIM) capacitor (see the entire document, specifically Fig. 1A+; [0002+], and as cited below), comprising (see alternate rejection of claim 1 below):
a first dielectric layer (112; Fig. 3H; [0040]) formed in a serpentine pattern on an underlying layer (100; Fig. 3H; [0038]);
a first type metal layer (118; Fig. 3H; [0043]) formed on the first dielectric layer (112; Fig. 3H; [0040]);
a second dielectric layer (120; Fig. 3H; [0043]) formed on the first type metal layer (118; Fig. 3H; [0043]);
a second type metal layer (122; Fig. 3H; [0043]) formed on the second dielectric layer (120; Fig. 3H; [0043]);
a first electrode (126; Fig. 3H; [0044]; 126 on the left side of Fig. 3H) electrically connected to the second type metal layer (122; Fig. 3H; [0044]); and
a second electrode (126; Fig. 3H; [0044]; 126 on the right side of Fig. 3H) electrically connected to the first type metal layer (118; Fig. 3H; [0044]).
Regarding claim 2, Wang teaches all of the features of claim 1.
Wang further comprising an Mx layer (110; Fig. 3H; [0039, 0044]) formed between the underlying layer (100; Fig. 3H; [0038]) and the MIM capacitor ({118, 120, 122}; Fig 3H).
Regarding claim 3, Wang teaches all of the features of claim 2.
Wang further teaches wherein a bottom surface of the first electrode (126; Fig. 3H; [0044]; 126 on the left side of Fig. 3H) contacts the Mx layer (110; Fig. 3H; [0039, 0044]), and a bottom surface of the second electrode (126; Fig. 3H; [0044]; 126 on the right side of Fig. 3H) contacts the first type metal layer (118; Fig. 3H; [0044]).
Regarding claim 4, Wang teaches all of the features of claim 1.
Wang further teaches wherein the first type metal layer (118; Fig. 3H; [0043-0044]) is a different type relative to the second type metal layer (122; Fig. 3H; [0043-0044]).
Regarding claim 5, Wang teaches all of the features of claim 1.
Wang further comprising a pillar (104; Fig. 3H; [0038]) formed between the underlying layer (100; Fig. 3H; [0038]) and the first dielectric layer (112; Fig. 3H; [0040]), wherein the first dielectric layer (112; Fig. 3H; [0040]), the first type metal layer (118; Fig. 3H; [0043]), the second dielectric layer (120; Fig. 3H; [0043]) and the second type metal layer (122; Fig. 3H; [0043]) have the serpentine pattern resulting from being formed to surround the pillar (104; Fig. 3H; [0038]).
Regarding claim 10, Wang teaches all of the features of claim 1.
Wang further comprising a first inner spacer (128; Fig. 3H; [0044]; 128 on the left side of Fig. 3H) formed between the first electrode (126; Fig. 3H; [0044]; 126 on the left side of Fig. 3H) and the first type metal layer (118; Fig. 3H; [0043]), and a second inner spacer (128; Fig. 3H; [0044]; 128 on the right side of Fig. 3H)formed between the second electrode (126; Fig. 3H; [0044]; 126 on the right side of Fig. 3H) and the second type metal layer (122; Fig. 3H; [0043]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claims 1 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (US 20230307492 A1; hereinafter Chou).
Regarding claim 1, Chou teaches a metal-insulator-metal (MIM) capacitor (see the entire document, specifically Fig. 1A+; [0003+], and as cited below), comprising (see alternate rejection of claim 1 above):
a first dielectric layer (114a; Fig. 37; see [0091, 0021]) formed in a serpentine pattern on an underlying layer (202; Fig. 37; [0023]);
a first type metal layer (102b; Fig. 37; see [0091,0024]) formed on the first dielectric layer (114a; Fig. 37; see [0091, 0021]);
a second dielectric layer (114b; Fig. 37; see [0091,0021]) formed on the first type metal layer (102b; Fig. 37; see [0091,0024]);
a second type metal layer (102c; Fig. 37; see [0091,0024]) formed on the second dielectric layer (114b; Fig. 37; see [0091,0021]);
a first electrode (106; Fig. 37; see [0096-0098, 0031-0032]) electrically connected to the second type metal layer (102c; Fig. 37; see [0091, 0024]); and
a second electrode (108; Fig. 37; see [0096-0098, 0031-0032]) electrically connected to the first type metal layer (102b; Fig. 37; see [0091, 0024]).
Regarding claim 6, Chou teaches all of the features of claim 1.
Chou further comprising a plurality of the first type metal layers (102b, 102d; Fig. 37; see [0091, 0024]) alternating with a plurality of the second type metal layers (102c, 102e; Fig. 37; see [0091, 0024]), wherein the first dielectric layer (114a, 114c; Fig. 37; see [0091, 0021]) and second dielectric layer (114b, 114d; Fig. 37; see [0091, 0021]) are present between each of the respective first type metal layers (102b, 102d; Fig. 37; see [0091, 0024]) and second type metal layers (102c, 102e; Fig. 37; see [0091, 0024]).
Regarding claim 7, Chou teaches all of the features of claim 6.
Chou further teaches wherein the first electrode (106; Fig. 37; see [0096-0098, 0031-0032]) is connected to the plurality of second type metal layers (102c, 102e; Fig. 37; see [0091, 0024]), and the second electrode (108; Fig. 37; see [0096-0098, 0031-0032]) is connected to the plurality of first type metal layers (102b, 102d; Fig. 37; see [0091, 0024]).
Regarding claim 8, Chou teaches all of the features of claim 6.
Chou further comprising a plurality of the pillars (stacks of {205, 206, 205, 206} on the left and right side of Fig. 37), wherein the first type metal layers (102b, 102d; Fig. 37; see [0091, 0024]), the second type metal layers (102c, 102e; Fig. 37; see [0091, 0024]) and the dielectric layers (1141, 114b, 114c, 114d; Fig. 37; see [0091, 0021]) completely fill an area between adjacent ones of the pillars (stacks of {205, 206, 205, 206} on the left and right side of Fig. 37).
Regarding claim 9, Chou teaches all of the features of claim 8.
Chou further teaches wherein a topmost one (102e; Fig. 37; see [0091, 0024]) of the second type metal layers (102c, 102e; Fig. 37; see [0091, 0024]) has a planar upper surface (top surface of 102e; Fig. 37; see [0091, 0024]) with a non-serpentine pattern (vertical section of 102e; Fig. 37; see [0091, 0024]) in the filled area between the pillars (stacks of {205, 206, 205, 206} on the left and right side of Fig. 37).
Conclusion
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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