DETAILED ACTION
This correspondence is in response to the communications received July 16, 2026. Claims 1-17 and 28-30 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-27 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II method claims, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on July 16, 2026.
Applicant's election with traverse of the restriction between structure and method groupings in the reply filed on July 16, 2026 is acknowledged. The traversal is on the ground(s) that no serious burden exists in examining both groupings since it is asserted that the independent structure and method claims are effectively indistinguishable. This is not found persuasive because as Examiner stated in the restriction, which followed the statutory frame work under 35 U.S.C. 121 & MPEP 806.05(f), a material difference was present as stated previously.
The requirement is still deemed proper and is therefore made FINAL.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1B, an integrated circuit (IC), comprising:
a semiconductor layer (108) comprising:
a first side (top side of 108) and a second side (lower side of 108) opposite the first side; and
a plurality of semiconductor devices (plural 110);
a signal interconnect structure (124) adjacent to the first side of the semiconductor layer (top side of 108),
the signal interconnect structure (124) comprising:
a plurality of first metal interconnects (130) each configured to transfer an input/output (I/O) signal to a coupled first semiconductor device (110) of the plurality of semiconductor devices (plural 110);
a power distribution network (PDN) interconnect structure (126) adjacent to the second side of the semiconductor layer (lower side of 108),
the PDN interconnect structure (126) comprising:
a plurality of second metal interconnects (130) each configured to transfer a power signal (135S, 135P, ¶ 0039); and
plurality of first vias (122) each extending through the semiconductor layer (partially through a portion of 108) and each coupled to a second metal interconnect (lower side vias 122, are coupled to 130, by way of several intervening conductors) of the plurality of second metal interconnects (130) and the signal interconnect structure (top side 122 connecting to 124).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (US 12,568,846) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901).
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Regarding claim 1, the prior art of Farooq discloses in Fig. 1A, an integrated circuit (IC) (“Integrated circuitry” and how this pertains to the inventive concepts are discussed throughout the disclosure, including, col. 3, lines 21-38), comprising:
a semiconductor layer (“the FEOL region 103 includes semiconductor layer 110 (e.g., formed of silicon (Si) or another suitable semiconductor material) in which active devices 112 are formed.”, col. 4, lines 47-50) comprising:
a first side (top side of 103) and a second side (lower side of 103) opposite the first side (top and lower sides oppose each other); and
a plurality of semiconductor devices (“active devices 112”, col. 4, line 50);
a signal interconnect structure (105, “The vias 116 interconnect the active devices 112 of the FEOL region 103 with signal routing in the second BEOL region 105”, col. 4, lines 53-55) adjacent to the first side of the semiconductor layer (105 on top surface of 103),
the signal interconnect structure (103) comprising:
a plurality of first metal interconnects (plural 120 shown, “metal line features 120”, col. 4, line 57) each configured to transfer an input/output (I/O) signal to a coupled first semiconductor device of the plurality of semiconductor devices (“The vias 116 interconnect the active devices 112 of the FEOL region 103 with signal routing in the second BEOL region 105. The second BEOL region 105, formed over the FEOL region 103, includes an ILD layer 118 with various metal line features 120 formed therein. The metal line features 120 include BEOL wiring which may be used for signal routing in the structure. A heat sink 122 is formed over the second BEOL region 105.”, col. 4, lines 55-60);
a power distribution network (PDN) interconnect structure (101, “first BEOL region 101 includes an interlayer dielectric (ILD) layer 106 with various metal line features 108 formed therein, where the metal line features 108 include BEOL wiring which may be used for a BSPDN structure.”, col. 4, lines 40-45, where “BSPDN” means “back side power distribution network”, see col. 3, lines 27-28) adjacent to the second side of the semiconductor layer (101 is adjacent to the lower side of 103),
the PDN interconnect structure (101) comprising:
a plurality of second metal interconnects (“metal line features 108”, col. 4, lines 43-44) each configured to transfer a power signal (“first BEOL region 101 includes an interlayer dielectric (ILD) layer 106 with various metal line features 108 formed therein, where the metal line features 108 include BEOL wiring which may be used for a BSPDN structure”, col. 4, lines 40-45, where “BSPDN” means “back side power distribution network”, see col. 3, lines 27-28. Thus, the power delivery network is based upon the conductors 108); and
plurality of first vias (“vias 114 and 116”, col. 4, line 51, where each via is interpreted to be the combination of stacked 114 and 116. There are a plurality of these 114/116 vias, as shown in Fig. 1A) each extending through the semiconductor layer (The 114/116 vias penetrate the semiconductor substrate 103 as can be seen in Fig. 1A) and each coupled to a second metal interconnect of the plurality of second metal interconnects and the signal interconnect structure (Some of the 114/116 vias couple to 108, and some other of the 114/116 vias couple to 120).
Farooq does not explicitly specify (italicized portion), “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal to a coupled first semiconductor device of the plurality of semiconductor devices”. So of the features captured by this limitation, the only feature not shown by Farooq, is that the signal is specifically an “input/output (I/O)” signal.
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The prior art of ‘901 discloses in Figs. 6A and 6B, in ¶ 0036, “FIG. 6A is a schematic illustrating a first portion of a process flow 200 to fabricate an electronic structure, including estimation of a power via. The first part of the process is to build devices (such as 202) and a thin BEOL 204 … base wafer 206 … FIG. 6B is a schematic illustrating a second portion of a process flow 200 to fabricate the electronic structure, including estimation of a power via. The fourth part of the process includes building a power / IO signal BEOL stack 216, that includes signals going off the die.” This satisfies that the signal being handled in the BEOL stack above the equivalent “semiconductor layer” (level including 202/210 in Fig. 6A and still viewable but not labeled in Fig. 6B), is a signal that is both power and an “IO signal” (where “IO” signifies “input output”, see Table 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, (italicized portion), “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal to a coupled first semiconductor device of the plurality of semiconductor devices”, as disclosed by ‘901 in the system of Farooq, for the purpose of shortening the pathway between the top BEOL wiring structure and active semiconductor region, by allowing the top BEOL wiring structure to have direct I/O access so as to be able to handle those signals directly to the active devices, thus shortening wiring lengths which would improve the signal by reducing at least RC delay in longer wiring pathways. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 1, 2, 11, 13, 14, 15, 16 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 11,041,211) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901).
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Regarding claim 1, the prior art of Jain discloses in (Examiner annotated) Figs. 2-2, Fig. 3-1, a integrated circuit (IC) (“Semiconductor dies 211, 212, and/or 414 may be from a same family of integrated circuits.”, col. 15, lines 33-34), comprising:
a semiconductor layer (portion “substrate 214”, of “Lower semiconductor die 212 includes a substrate 214”, col. 8, line 48) comprising:
a first side (lower side of 214) and a second side (upper side of 214) opposite the first side (lower and upper sides oppose each other); and
a plurality of semiconductor devices (“Lower semiconductor die 212 may include circuitry components, such as may include one or more transistors 223, as well as other circuitry components, as generally depicted for purposes of clarity and not limitation. In an example, gates and gate dielectrics may be located above an upper surface 209 of substrate 214.”, col. 8, lines 59-64, hereinafter referred to as ‘FSD’);
a signal interconnect structure (annotated SIS, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 238, col. 11, lines 14, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13) adjacent to the first side of the first semiconductor layer (SIS are adjacent to lower surface of 214), the
signal interconnect structure (SIS) comprising:
a plurality of first metal interconnects (In SIS, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) each configured to transfer an input/output (I/O) signal (In one interpretation, an “IO signal” going through metal levels in SIS from 234 to the devices 223 in 214, would be input from 234 to 214 on a literal level and interpretation. A Secondary reference will be used below to address the explicit teaching of this concept.) to a coupled first semiconductor device (“transistors 223”) of the plurality of the semiconductor devices (of the aforementioned FSD);
a power distribution network (PDN) interconnect structure (annotated PDN, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 228, col. 9, lines 54, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13) adjacent to the second side of
the semiconductor layer (PDN formed on the upper surface side of 214),
the PDN interconnect structure (PDN) comprising:
a plurality of second metal interconnects (In PDN, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) each configured to transfer a power signal (At least portion M5 carries power, “a power distribution network (“PDN”) metal layer M5”, col. 7, lines 38-39); and
a plurality of first vias (“TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51) each extending through the semiconductor layer (through 214) and each coupled to a second metal interconnect of the plurality of second metal interconnects (211 couples to M1 of 228 of aforementioned metal lines of the “second metal interconnects” of the PDN) and the signal interconnect structure (221 also connects to M11 of 239 of annotated SIS).
Jain discloses each feature except the italicized portion, “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal”.
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The prior art of ‘901 discloses in Figs. 6A and 6B, in ¶ 0036, “FIG. 6A is a schematic illustrating a first portion of a process flow 200 to fabricate an electronic structure, including estimation of a power via. The first part of the process is to build devices (such as 202) and a thin BEOL 204 … base wafer 206 … FIG. 6B is a schematic illustrating a second portion of a process flow 200 to fabricate the electronic structure, including estimation of a power via. The fourth part of the process includes building a power / IO signal BEOL stack 216, that includes signals going off the die.” This satisfies that the signal being handled in the BEOL stack above the equivalent “semiconductor layer” (level including 202/210 in Fig. 6A and still viewable but not labeled in Fig. 6B), is a signal that is both power and an “IO signal” (where “IO” signifies “input output”, see Table 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, (italicized portion), “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal”, as disclosed by ‘901 in the system of Jain, for the purpose of allowing the all the chips I/O access so as to be able to handle those signals and add functionality to the signal handling capability of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Jain et al. disclose the IC of claim 1, and Jain discloses in Fig. 2-2, wherein:
the signal interconnect structure (SIS) comprises a plurality of first metallization layers (In SIS, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) comprising:
the plurality of first metal interconnects (In SIS, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52); and
a plurality of second vias (‘TSV 222’, discussed in, “Upper semiconductor die 211 includes a substrate 213 having a TSV 222. Even though only one TSV 222 is illustratively depicted for purposes of clarity, substrate 213 may include more than one TSV.”, col. 6, lines 61-64) interconnecting the plurality of second metal interconnects (222 connect to the metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, which reside within PDN); and
the PDN interconnect structure (annotated PDN) comprises a plurality of second metallization layers (the metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, which reside within PDN) comprising:
the plurality of second metal interconnects (the metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, which reside within PDN); and
a plurality of third vias (The vias shown in Fig. 2-2, as the vertical connectors between M metal levels, and discussed in , “In a region of chimney 227, lower and upper metalization and ILD levels 228 and 229 are used to provide a low resistivity path by increasing conductive via density in such chimney region for purposes of metalization-level-to-metalization-level electrical conductivity. Between lower and upper metalization and ILD levels 228 and 229 is a PDN metal layer M5 and corresponding ILD level ILD5. Likewise, in a region of chimney 227 PDN metal layer M5 with ILD level ILD5 are used to provide a low vertical resistivity path by increasing conductive via density in such chimney region for purposes of metalization-level-to-metalization-level electrical conductivity.”, col. 10, lines 23-34) interconnecting the plurality of second metal interconnects (noted vias interconnect the metal levels M).
Regarding claim 11, the prior art of Jain et al. disclose the IC of claim 1, and Jain discloses in Fig. 2-2, further comprising:
a first die structure (interpreted to be both “substrate 214” and annotated SIS, where “Lower semiconductor die 212 includes a substrate 214”, col. 8, line 48) comprising the semiconductor layer (previously noted 214, “Lower semiconductor die 212 includes a substrate 214”, col. 8, line 48) and the signal interconnect structure (previously noted SIS, annotated SIS, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 238, col. 11, lines 14, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13); and
a second die (The “second die” has been interpreted to be the collection of elements of “substrate 213” and examiner annotated features of ‘PDN’. Where the ‘die’ aspect is addressed by “semiconductor die 211 includes a substrate 213”, col. 6, line 61) structure comprising the PDN interconnect structure (annotated PDN, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 228, col. 9, lines 54, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13);
wherein the first die structure (214 and SIS) is bonded to the second die structure (213 and PDN) to couple each second metal interconnect of the plurality of second metal interconnects (In PDN, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) to a first via of the plurality of first vias (noted metals in PDN, as shown in Fig. 2-2, couple to “TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51).
Regarding claim 13, the prior art of Jain et al. disclose the IC of claim 11, wherein each second metal interconnect of the plurality of second metal interconnects (M1 of the metal layers, col. 9, lines 42-52, in annotated PDN in Fig. 2-2 of Jain) is directly bonded to a first via of the plurality of first vias (M1 directly bonds to TSV 221, col. 9, line 45-50).
Regarding claim 14, the prior art of Jain et al. disclose the IC of claim 1, wherein:
the semiconductor layer (214, “Lower semiconductor die 212 includes a substrate 214”, col. 8, line 48) extends in a first direction (X of the horizontal directions of X or Y directions, as 214 is a die, which is a 3D object that has dimensions in all three direction of X, Y and Z);
the second side (upper surface of 214) is opposite the first side (lower surface of 214) in a second direction orthogonal to the first direction (vertical direction separates upper and lower surfaces of 214);
the plurality of first vias each extend through the semiconductor layer in the second direction (vias “TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51); and
a plurality of second vias each extend through the semiconductor layer in the second direction (vias “TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51. So selecting one of the further plurality of vias, where they in the range of more than one, that includes many, so in the scheme of large amounts of data lines in a high density microelectronic device, such as “Conductive Vias 303” as can be seen in Fig. 3-1. The term “second” of “second vias” is merely a label, and so if there are two groups of plurality of vias, then the Jain disclosure satisfies the limitation).
Regarding claim 15, the prior art of Jain et al. disclose the IC of claim 1,and Jain discloses in Figs. 2-2, 3-1, wherein the plurality of first vias comprises a plurality of first through-silicon vias (TSVs) (“TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51).
Regarding claim 16, the prior art of Jain et al. disclose the IC of claim 3, wherein the plurality of second vias comprises a plurality of second through-silicon vias (TSVs) (vias “TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51. So selecting one of the further plurality of vias, where they in the range of more than one, that includes many, so in the scheme of large amounts of data lines in a high density microelectronic device, such as “Conductive Vias 303” as can be seen in Fig. 3-1. The term “second” of “second vias” is merely a label, and so if there are two groups of plurality of vias, then the Jain disclosure satisfies the limitation).
Regarding claim 17, the prior art of Jain et al. disclose the IC of claim 1 integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (Farooq ‘901 discloses in ¶ 0067, wherein stacked integrated circuits can be utilized for use in various device applications, such as a mobile phone, processors, cellular network device, etc.).
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Regarding claim 28, the prior art of Jain discloses in (Examiner annotated) Figs. 2-2, Fig. 3-1, a three-dimensional (3D) integrated circuit (IC) (3DIC) (“Semiconductor dies 211, 212, and/or 414 may be from a same family of integrated circuits.”, col. 15, lines 33-34. The “3D” aspect being addressed by the stacked nature of plural chips as shown in Fig. 2-2.), comprising:
a first IC (The “first IC” has been interpreted to be the collection of elements of “substrate 214”, examiner annotated features of ‘SIS’ and ‘PDN’. Where the ‘IC’ aspect associated with the die 214 and the surrounding components are generally considered “integrated circuits”, col. 15, lines 33-34), comprising:
a first semiconductor layer (portion “substrate 214”, of “Lower semiconductor die 212 includes a substrate 214”, col. 8, line 48) comprising:
a first side (lower surface of 214) and a second side (upper surface of 214) opposite the first side (lower and upper surfaces oppose each other); and
a plurality of first semiconductor devices (“Lower semiconductor die 212 may include circuitry components, such as may include one or more transistors 223, as well as other circuitry components, as generally depicted for purposes of clarity and not limitation. In an example, gates and gate dielectrics may be located above an upper surface 209 of substrate 214.”, col. 8, lines 59-64, hereinafter referred to as ‘FSD’);
a signal interconnect structure (annotated SIS, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 238, col. 11, lines 14, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13) adjacent to the first side of the first semiconductor layer (SIS are adjacent to lower surface of 214),
the signal interconnect structure (SIS) comprising:
a plurality of first metal interconnects (In SIS, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) each configured to transfer an input/output (I/O) signal (In one interpretation, an “IO signal” going through metal levels in SIS from 234 to the devices 223 in 214, would be input from 234 to 214 on a literal level and interpretation. A Secondary reference will be used below to address the explicit teaching of this concept.) to a coupled first semiconductor device (“transistors 223”) of the plurality of first semiconductor devices (of the aforementioned FSD);
a power distribution network (PDN) interconnect structure (annotated PDN, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 228, col. 9, lines 54, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13) adjacent to the second side of the first semiconductor layer (PDN formed on the upper surface side of 214),
the PDN interconnect structure (annotated PDN) comprising:
a plurality of second metal interconnects (In PDN, the metal levels M1, M3, , M5, M9, M11, col. 9, lines 42-52) each configured to transfer a power signal (At least portion M5 carries power, “a power distribution network (“PDN”) metal layer M5”, col. 7, lines 38-39); and
a plurality of first vias (“TSV 221”, where plurality are discussed, “Even though only one TSV 221 is illustratively depicted for purposes of clarity, substrate 214 may include more than one TSV.”, col. 8, lines 49-51) each extending through the first semiconductor layer (through 214) and each coupled to a second metal interconnect of the plurality of second metal interconnects (211 couples to M1 of 228 of aforementioned metal lines of the “second metal interconnects” of the PDN) and the signal interconnect structure (221 also connects to M11 of 239 of annotated SIS); and
a second IC (The “second IC” has been interpreted to be the collection of elements of “substrate 213”, examiner annotated features of ‘PDN’ and ‘TIS’. Where the ‘IC’ aspect associated with the die 213 and the surrounding components are generally considered “integrated circuits”, col. 15, lines 33-34), comprising:
a second semiconductor layer (portion “substrate 213”, of “Upper semiconductor die 211 includes a substrate 213 having a TSV 222. Even though only one TSV 222 is illustratively depicted for purposes of clarity, substrate 213 may include more than one TSV.”, col. 6, lines 61-64);
a third interconnect structure (annotated ‘TIS’, which includes metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52, and interlevel dielectric ILD 218, col. 7, line 27, ILD5, col. 11, line 16, 219, col. 7, line 32, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13) adjacent to the second semiconductor layer (TIS adjacent to top surface of 213),
the third interconnect structure (TIS) comprising:
a plurality of third metal interconnects (In TIS, metal levels M1, M3, M5, M9, M11, col. 9, lines 42-52) each comprising a power signal node (In TIS, at least portion M5 carries power, “a power distribution network (“PDN”) metal layer M5”, col. 7, lines 38-39); and
a plurality of second vias (‘TSV 222’, discussed in, “Upper semiconductor die 211 includes a substrate 213 having a TSV 222. Even though only one TSV 222 is illustratively depicted for purposes of clarity, substrate 213 may include more than one TSV.”, col. 6, lines 61-64) each extending through the second semiconductor layer (through 213) and each coupled to a third metal interconnect of the plurality of third metal interconnects (222 couples to M1 of aforementioned “third metal interconnects” in TIS);
wherein:
the first IC (214) is coupled to the second IC (213), by each of the plurality of second metal interconnects (M1-M11 in PDN) in the second IC (213) being coupled to a second via (222) of the plurality of second vias (discussed in col. 6, lines 61-64) in the first IC (214) to couple each of the plurality of second metal interconnects (M1-M11 in PDN) to a third metal interconnect (M1 of TIS) of the plurality of third metal interconnects in the second IC (M1-M11 in TIS).
Jain discloses each feature except the italicized portion, “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal”.
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The prior art of ‘901 discloses in Figs. 6A and 6B, in ¶ 0036, “FIG. 6A is a schematic illustrating a first portion of a process flow 200 to fabricate an electronic structure, including estimation of a power via. The first part of the process is to build devices (such as 202) and a thin BEOL 204 … base wafer 206 … FIG. 6B is a schematic illustrating a second portion of a process flow 200 to fabricate the electronic structure, including estimation of a power via. The fourth part of the process includes building a power / IO signal BEOL stack 216, that includes signals going off the die.” This satisfies that the signal being handled in the BEOL stack above the equivalent “semiconductor layer” (level including 202/210 in Fig. 6A and still viewable but not labeled in Fig. 6B), is a signal that is both power and an “IO signal” (where “IO” signifies “input output”, see Table 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, (italicized portion), “a plurality of first metal interconnects each configured to transfer an input/output (I/O) signal”, as disclosed by ‘901 in the system of Jain, for the purpose of allowing the all the chips I/O access so as to be able to handle those signals and add functionality to the signal handling capability of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 11,041,211) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901) in view of Ding et al. (US 2022/0336326).
Regarding claim 3, the prior art of Jain et al. disclose the IC of claim 1, however Jain does not show multiple vias in the drawing with connections to plural mentalizations in the drawings, so Jain does not explicitly disclose,
“wherein the PDN interconnect structure further comprises a plurality of third metal interconnects; and
further comprising:
a plurality of second vias each extending through the semiconductor layer and each coupled to a third metal interconnect of the plurality of third metal interconnects and a first metal interconnect of the plurality of first metal interconnects.”
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Ding discloses in Fig. 1 and in ¶ 0048, “The first through via 141 may be configured to “communicate” (e.g., transmit and/or receive) a non-power signal (e.g., a signal other than a power signal—hereafter simply, a “signal”), and the second through via 142 may be configured to communicate a power signal—hereafter simply, “power”).” This teaching shows the use of plural vias (141 and 142, ¶ 0014) going through an equivalent semiconductor layer (110, ¶ 0014), where the vias connect to metallization structures equivalent to “metal interconnects” (metal levels DL, WL1-WL4, PL shown in IL1-IL12, ¶ 0014). By combining this teaching with Jain, the extra set of through via and metal interconnects would satisfy the limitation. Further as metallization and insulator stack region would be equivalent to the PDN as claimed, one of the vias would then pass through semiconductor layer (110) and make contact with the metallization/metal interconnect of the lower SIS metal interconnect, which is the claimed “a first metal interconnect of the plurality of first metal interconnects”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the PDN interconnect structure further comprises a plurality of third metal interconnects; and
further comprising:
a plurality of second vias each extending through the semiconductor layer and each coupled to a third metal interconnect of the plurality of third metal interconnects and a first metal interconnect of the plurality of first metal interconnects.”, as disclosed by Ding in the system of Jain, for the purpose of allowing for a variety of signals to pass through the system, such as some for power and some for data. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 6, 9 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 11,041,211) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901) in view of Chen et al. (US 2020/0402903).
Regarding claim 6, the prior art of Jain et al. disclose the IC of claim 1, however Jain does not disclose, “further comprising one or more capacitors in the PDN interconnect structure and each coupled to a second metal interconnect of the plurality of second metal interconnects.”
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Chen discloses in Fig. 3, a metallization stack structure with interlevel dielectrics, which include element 27, which represents a capacitive structure, ¶ 0026. This configuration is equivalent to the PDN interconnect structure, where “the second metal interconnects” are equivalent to the metals shown including 20-2, 22-2, which have a dielectric 27 therebetween, “Between the two layers of electrodes 20-2, 22-2, at least one dielectric layer 27 which may comprise at least one layer of insulating material, high dielectric material, nitride film, etc. may be formed to increase capacitance of the capacitors 131-1, 131-2, 131-n.”, ¶ 0026.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising one or more capacitors in the PDN interconnect structure and each coupled to a second metal interconnect of the plurality of second metal interconnects.”, as disclosed by Chen in the system of Jain, for the purpose of allowing for signal manipulation to improve the signal for use in the internal devices of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 9, the prior art of Jain et al. disclose the IC of claim 6, and the combination rejection of claim 6 discloses,
wherein:
the PDN interconnect structure (Fig. 2-2 of Jain, shows annotated ‘PDN’) comprises a dielectric layer (interlevel dielectric ILD 228, col. 9, lines 54, ILD5, col. 11, line 16, 239, col. 11, line 12, ILD11, “inter-level dielectric layers … ILD1-ILD11”, col. 16, lines 11-13); and
at least one capacitor of the one or more capacitors comprises at least one dielectric capacitor in the dielectric layer (the combination rejection modifies PDN of Jain’s Fig. 2-2, by incorporating the capacitor of Chen’s Fig. 3, which has two electrodes 20-2, 22-2 which sandwich “dielectric layer 27”, ¶ 0026).
Regarding claim 29, the prior art of Jain et al. disclose the 3DIC of claim 28, however Jain does not disclose, “further comprising one or more capacitors in the PDN interconnect structure of the first IC and each coupled to a second metal interconnect of the plurality of second metal interconnects in the first IC.”
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Chen discloses in Fig. 3, a metallization stack structure with interlevel dielectrics, which include element 27, which represents a capacitive structure, ¶ 0026. This configuration is equivalent to the PDN interconnect structure, where “the second metal interconnects” are equivalent to the metals shown including 20-2, 22-2, which have a dielectric 27 therebetween, “Between the two layers of electrodes 20-2, 22-2, at least one dielectric layer 27 which may comprise at least one layer of insulating material, high dielectric material, nitride film, etc. may be formed to increase capacitance of the capacitors 131-1, 131-2, 131-n.”, ¶ 0026.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising one or more capacitors in the PDN interconnect structure of the first IC and each coupled to a second metal interconnect of the plurality of second metal interconnects in the first IC.”, as disclosed by Chen in the system of Jain, for the purpose of allowing for signal manipulation to improve the signal for use in the internal devices of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 11,041,211) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901) in view of Chen et al. (US 2020/0402903) in view of Chu et al. (US 2016/0204190).
Regarding claim 10, the prior art of Jain et al. disclose the IC of claim 9, however Chen does not disclose that the capacitor has, “wherein the dielectric layer comprises a silicon oxide layer.” Chen discloses that dielectric 27 has dielectric materials including, “Between the two layers of electrodes 20-2, 22-2, at least one dielectric layer 27 which may comprise at least one layer of insulating material, high dielectric material, nitride film, etc.”, ¶ 0026. Clearly, a capacitor may include a dielectric that is a common “insulating material” of a silicon oxide. The following reference will teach this aspect.
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Chu discloses in Fig. 2, wherein the dielectric layer comprises a silicon oxide layer (“capacitor 102”, ¶ 0014, “The capacitor dielectric layer 116 comprises … silicon dioxide”, ¶ 0043).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the dielectric layer comprises a silicon oxide layer”, as disclosed by Chu in the system of Jain, for the purpose of allowing for charge build up between the two capacitor electrodes for use in signal manipulation in the metallization and interlevel dielectric structure. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 11,041,211) in view of Farooq et al. (US 2023/0230901, hereinafter referred to as ‘901) in view of Law et al. (US 2010/0225002).
Regarding claim 12, the prior art of Jain et al. disclose the IC of claim 11, however Jain does not disclose, “further comprising a metal bump layer between the PDN interconnect structure and the semiconductor layer, the metal bump layer comprising a plurality of metal bumps each coupled to a second metal interconnect of the plurality of second metal interconnects and a first via of the plurality of first vias.”
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Law discloses in Fig. 5, where equivalent “metal bump structure” is 405/407 between each of the chips/metallization plus ILD structures, ¶ 0039, “connections (e.g., conductive layer 405 and ENIG layer 407) between the first die 501, the second die 505, and the third die 507.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising a metal bump layer between the PDN interconnect structure and the semiconductor layer, the metal bump layer comprising a plurality of metal bumps each coupled to a second metal interconnect of the plurality of second metal interconnects and a first via of the plurality of first vias.”, as disclosed by Chu in the system of Jain, for the purpose of allowing for charge build up between the two capacitor electrodes for use in signal manipulation in the metallization and interlevel dielectric structure. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 4, 5, 7, 8 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of Jain (US 11,041,211) and Ding et al. (US 2022/0336326) fail to show that specific arrangement where all of the third metal interconnects are specifically connected to signal node that is not a power signal node, “wherein each of the plurality of third metal interconnects are not coupled to a power signal node.”
Regarding claim 5, the prior art of Jain (US 11,041,211) and Ding et al. (US 2022/0336326) fail to show that specific arrangement where the third vias make two specific connections, including to a second vias, “wherein the PDN interconnect structure further comprises a plurality of third vias each coupled to a second metal interconnect of the plurality of second metal interconnects and a second via of the plurality of second vias.”
Regarding claim 7, the prior art of Jain (US 11,041,211) and Ding et al. (US 2022/0336326) fail to show that specific arrangement where,
“the PDN interconnect structure comprises a silicon layer; and
at least one capacitor of the one or more capacitors comprises at least one silicon capacitor in the silicon layer.”
Claim 8 has been objected to, for the reason that claim 8 depends from claim 7.
Regarding claim 30, the prior art of Jain (US 11,041,211) and Ding et al. (US 2022/0336326) fail to show that specific arrangement of where the capacitor is located and which specific features the capacitor connects to, “least one capacitor … further coupled to a second via of the plurality of second vias … to couple the at least one capacitor to at least one third metal interconnect”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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