DETAILED ACTION
This action is responsive to the application No. 18/609,426 filed on March 19, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the interdielectric layers (plural), the hexagonal holes, the silicon oxide filling the trenches, and the sensor comprising a plurality of photodiodes, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3-12 objected to because of the following informalities:
In Claims 3-12, the preambles should begin with “The method according to claim…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites performing an etch to form a plurality of raised portions of semiconductor material. Reciting “raised portions” implies part of the surface is higher than the surrounding, un-etched, flat surface of the substrate. Fig. 4C apparently shows the structure after etching the trenches 12, however there are no raised portions shown in Fig. 4C making it unclear what applicant regards as “raised portions”. For the purpose of examination, this will be treated as etching trenches in the surface since the etching does not appear to form “raised portions” of the surface.
Claim 12 recites filling the trenches with silicon oxide to form a layer of an effective medium at the surface of the wafer, wherein the effective medium has a refractive index between that of silicon oxide and that of silicon. This limitation is confusing because a trench filled with silicon oxide, understood to be an effective medium, will have a refractive index of silicon oxide, not “between that of silicon oxide and that of silicon”. It is unclear how depositing silicon oxide in a trench results in a refractive index greater than that of silicon oxide since the range recites “between”, i.e. greater than, not including. In addition, the refractive index of silicon oxide depends on the process used to form the silicon oxide and its crystallinity (amorphous or single crystal, e.g. quartz), the refractive index of silicon depends on the crystallinity of the silicon (e.g. single crystal vs. polysilicon vs. amorphous), and the index of refraction also depends on the wavelength, none of which are recited making it unclear under what conditions the range of refractive index corresponds to. For the purpose of examination this will be treated as silicon oxide having a refractive index of silicon oxide, silicon oxide being the “effective medium” the trenches are filled with.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al. (US 2018/0358488).
(Re Claim 1) Yamashita teaches a method of forming a photodiode, the method comprising (see Figs. 1A-1J and supporting text):
providing a semiconductor wafer comprising a semiconductor layer (102, ¶13);
performing a first doping step to form a first well in the semiconductor layer having a first type of doping (Figs. 1B-1C, 106/112);
performing a second doping step to form a second well having a second type of doping, so as to form a pn-junction of the photodiode between the first well and the second well (Fig. 1C, 124, ¶¶15-17);
performing a shallow trench isolation etch to form a plurality of trenches in a surface of the semiconductor layer in the second well (Fig. 1D, ¶¶18,40);
performing a third doping step by injecting dopants at a first angle relative to the surface of the wafer in order to increase a doping concentration of the second type of doping along the sides of the trenches in the second well; performing a fourth doping step by injecting dopants at a second angle relative to the surface of the wafer in order to increase a doping concentration of the second type of doping at the bottom of the trenches in the second well; performing a fifth doping step to increase a doping concentration of the second type of doping at the surface of the semiconductor layer between the trenches in the second well (ion implant(s) 141 in Fig. 1E forms doped region 128, thereby increasing the doping concentration everywhere (tops, bottoms, sidewalls, etc.) within region 128, ¶20, the claim language does not preclude this treatment, the claim does not require these steps to be performed at different angles and the recited third-fifth doping steps may be performed simultaneously or sequentially, e.g. the third step is for a first duration of the implant process, the fourth for a second duration of the implant process, etc, all at any angle, same or different); and
forming a first contact for contacting the first well and forming a second contact for contacting the second well in order to apply a voltage across the pn-junction when in use (Fig. 1H, contacts 154/156).
(Re Claim 2) Yamashita teaches a method of forming a photodiode, the method comprising (see Figs. 1A-1J and supporting text):
providing a semiconductor wafer comprising a semiconductor layer (102, ¶13);
performing a first doping step to form a first well in the semiconductor layer having a first type of doping Figs. 1B-1C, 106/112);
performing a second doping step to form a second well having a second type of doping, so as to form a pn-junction of the photodiode between the first well and the second well (Fig. 1C, 124, ¶¶15-17);
performing a shallow trench isolation etch to form a plurality of raised portions of semiconductor material in a surface of the semiconductor layer in the second well (Fig. 1D, ¶¶18,40);
performing a third doping step by injecting dopants at a first angle relative to the surface of the wafer in order to increase a doping concentration of the second type of doping at along the sides of the raised portions in the second well; performing a fourth doping step by injecting dopants at a second angle relative to the surface of the wafer in order to increase a doping concentration of the second type of doping between the raised portions in the second well; performing a fifth doping step to increase a doping concentration of the second type of doping at the surface of the semiconductor layer at a top of the raised portions in the second well (ion implant(s) 141 in Fig. 1E forms doped region 128, thereby increasing the doping concentration everywhere (tops, bottoms, sidewalls, etc.) within region 128, ¶20, the claim language does not preclude this treatment, the claim does not require these steps to be performed at different angles and the recited third-fifth doping steps may be performed simultaneously or sequentially, e.g. the third step is for a first duration of the implant process, the fourth for a second duration of the implant process, etc, all at any angle, same or different); and
forming a first contact for contacting the first well and forming a second contact for contacting the second well in order to apply a voltage across the pn-junction when in use (Fig. 1H, contacts 154/156).
(Re Claim 7) wherein the second, third, fourth and fifth doping steps are performed using a same mask (the doping is performed using “a mask” (singular), ¶20).
(Re Claim 12, also see §112 above) further comprising filling the trenches with silicon oxide to form a layer of an effective medium at the surface of the wafer, wherein the effective medium has a refractive index between that of silicon oxide and that of silicon (trenches are filled with silicon oxide 152 in Fig. 1H, silicon oxide having a refractive index of silicon oxide, while the surrounding silicon will have a refractive index of silicon).
(Re Claim 13) Yamashita teaches a semiconductor structure comprising a photodiode formed according to the method of claim 1 (Fig. 1H).
Claim 13 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed doping steps need not be formed by the process of “injecting dopants” and may be formed by any means for forming a doped region using any number of doping steps. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Rhodes (US 2002/0140668), Stevens (US 2010/0140668), and Gupta et al. (US 2006/0208202).
(Re Claim 3) wherein the first angle is in the range of 30° to 45° with respect to a normal to the surface.
(Re Claim 4) wherein the second angle is in the range of 0° to 15° with respect to a normal to the surface.
(Re Claim 5) wherein at least the third doping step is performed at four or more different rotation angles about a normal to the surface of the wafer.
(Re Claim 6) wherein the third doping step comprises injecting the dopants with a first injection energy, and wherein the fourth doping step comprises injecting the dopants with a second injection energy, wherein the first injection energy is greater than the second injection energy.
Yamashita is silent regarding ranges of angles for each doping step and implant energy for a third and fourth. A PHOSITA desiring to make and use Yamashita’s device would be motivated to look to related art to teach details of ion implanting trenches. Related art from Rhodes teaches when ion implanting trenches, a series of angled implants at different angles are used to ensure all surfaces are sufficiently implanted (Figs. 8-10 and ¶59). Related art from Stevens also teaches implanting trenches at a plurality of different angles to ensure all of the exposed trench surfaces are sufficiently and uniformly implanted (¶40). Related art from Gupta teaches doping trenches by using a plurality of different angles and energy to uniformly dope the surfaces of a trench, recognizing that the angled implants require higher energy than implanting at normal incidence (see Figs. 13-15 and ¶¶60-62). Since ion implant is a ballistic, line-of-sight, type of doping process, the ions are injected into the material where the ion beam is directed, along the axis of the beam. The shallower the angle is with respect to a surface, the more the ions will bounce or reflect off of the surface rather than penetrate into the surface. In order to implant the sidewall surfaces of the trenches, one would orient the ion beam at different angles, preferably perpendicular to (or close to perpendicular) each surface of the trench. To implant into the bottom surface of the trench and/or the top surface of the substrate, an implant at normal incidence, or at a slight angle to avoid channeling, would be preferred, while the sidewalls of the trenches require implanting at different smaller/shallower angles. When implanting at angles other than normal, especially smaller/shallower angles, the implant mask and the trenches can cause shadowing. In order to completely implant the trench surfaces, recognizing the smaller angles necessary to orient the ion beam close to normal to the sidewall, will also result in shadowing. Therefore, some of the implanting needs to be at less than ideal angles, using small/shallow angles relative to the sidewall. In order to effectively implant the same amount of ions into the surface when using small/shallow angles, higher energy is required to accomplish the same effective implant. A PHOSITA would understand this and would find it obvious to use as many implants at as many different angles as necessary to fully and successfully implant all of the different surfaces while accounting for shadowing (e.g. when using less than optimal angles, compensating with higher energy). The number of implants, the angles used for each, and the appropriate energy, would be obvious to optimize, and ascertainable through routine experimentation, also see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In view of the prior art, a PHOSITA would understand, and find it obvious, that in order to completely and uniformly implant all of the different trench/substrate surfaces, it is necessary to perform the implanting at different angles for each surface, and compensate with higher energy as needed, especially at smaller/shallower angles.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Rao (US 2007/0158790) and Webster et al. (US 2013/0193546).
(Re Claim 8) wherein the second, third, fourth and fifth doping steps are performed so as to create a continuously falling doping concentration from the trenches to the pn-junction.
Yamashita is silent regarding a continuously falling doping concentration from the trenches to the pn-junction. Based on the manner in which the doped wells and trenches are formed, by using successive implants from the top surface, followed by annealing to diffuse the dopants into the structure, it is obvious the concentration profile will continuously fall from the trenches. Region 128, having the highest concentration, in particular, initially at the surface, region 124 having a lower concentration, while the annealing/diffusing step will provide a continuously falling transition since the diffusion is driven by a concentration gradient (Fick’s laws), to the pn junction. It is obvious there will be no sharp or abrupt steps or discontinuity based on performing the conventional ion implants followed by annealing/diffusion steps.
Further still, a continuously falling dopant concentration in a photodiode is advantageous according to Rao and Webster. Rao teaches a continuously falling concentration, i.e. graded, is advantageous for better visual quality including pixel resolution and color sensitivity for imaging ICs (abstract, Fig. 5b, ¶13). Webster also recognizes advantages of using a graded doping concentration which accelerates carriers towards the junction, reduces recombination, increases avalanche generation and thus increases the detection efficiency (¶¶145-170, Figs. 17-18). A PHOSITA would be motivated to use a continuously falling dopant concentration through regions 128/124 for the advantages identified by Rao and Webster.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Kwak (US 2007/0080413) and Stark (US 2018/0108799).
(Re Claim 9) wherein the semiconductor wafer is a silicon wafer comprising an epitaxial layer within which the first well and the second well are formed.
While Yamashita discloses the device may be formed on a substrate with a doped epitaxial layer (¶13), Yamashita does not specifically disclose whether the wells are actually formed in the epi-layer. A PHOSITA would be motivated to look to related art to teach where to form the wells when forming photodetector devices. Related art from Kwak teaches forming the photodiode in the epitaxial layer (see Figs. 3-4G). Related art from Stark also teaches forming the wells of the photodiode in the epitaxial layer 200 (Fig. 2, ¶41). In view of the prior art, a PHOSITA would find it obvious to form the wells of Yamashita’s photodiode in the epitaxial layer. Forming the wells of a photodiode in an epitaxial layer rather than bulk silicon minimizes defect densities, which critically reduces noise-inducing leakage currents.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Gaebler (US 2017/0025451).
(Re Claim 10) forming a backend stack comprising a plurality of metal layers separated by interdielectric layers, and a nitride passivation layer; and locally removing the nitride passivation layer in a region overlapping the pn-junction.
Yamashitta forms a plurality of metal layers in an interlayer dielectric layer (Fig. 1H), however is silent regarding a plurality of dielectric layers separating the metal layers and lacks a nitride passivation layer. A PHOSITA desiring to make, use, and improve upon Yamashita’s device would be motivated to look to related art for possible modifications for improvements. Related art from Gaebler teaches forming a multilayer metallization structure 7/25 in a plurality of dielectric layers 12 and forms a nitride passivation 13 (¶60) on the top of the structure and then locally removes it from the region overlapping the photodiode sensing region 6 (see Figs. 1-9 and supporting text). Employing a plurality of metallization layers in a plurality of ILD layers is well known in the art and allows for signal routing in/out of the structure. With respect to the nitride passivation, forming passivation layers on devices is also well known in the art. The passivation provides protection and insulation, however, Gaebler recognizes that silicon nitride absorbs UV light, thus when detecting UV is desirable, it is beneficial to remove the nitride passivation over the sensing region (¶¶60-76). In view of Gaebler, a PHOSITA would find it obvious to use a multilayer metallization/ILD interconnect structure to provide signal routing, while the silicon nitride passivation advantageously provides protection and insulation and shields other parts of the device from UV light, while the opening in the passivation allows the UV light to reach the sensing region.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Gäbler (US 2019/0393251).
(Re Claim 11) Yamashita is silent wherein the trenches comprise circular or hexagonal holes having a width in the range of 220 nm to 350 nm and a spacing from an adjacent hole in the range of 70 nm to 210 nm.
Yamashita teaches the anti-reflection structure 124 may be a variety of shapes (¶18) and the individual features may have sizes of less than 500 nm, proportional to the wavelength of interest (¶19). A PHOSITA desiring to make, use, and improve upon Yamashita’s antireflection structure would be motivated to look to related art to teach related antireflection structures for improved light absorption. Related art from Gäbler teaches similar antireflection structures for photodetectors (see Figs. 1, 3, and 5-9 and supporting text). Gäbler teaches (¶37) the pattern can be formed by hexagon shapes in a hexagonal arrangement, or squares in a quadratic arrangement, and that any other shapes and arrangements are possible. A width of the trenches may be in the range of 250 nm to 310 nm, and the minimum spacing between trenches may be in the range of 190 nm to 250 nm. The width and spacing selected based on the desired wavelength of light (¶¶48-51). In view of Gäbler, a PHOSITA would find it obvious to try a hexagonal shape and select a width and spacing within the claimed range in order to optimize absorption within the UV range.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2018/0358488) in view of Stark (US 2018/0108799).
(Re Claim 14) Yamashita teaches a semiconductor structure comprising a photodiode formed according to the method of claim 1 (Fig. 1H).
Yamashita is silent regarding a plurality of photodiodes. Related art from Stark teaches photodiodes may be arranged in an array (Figs. 6a-6b, 10a-10c, ¶¶91-100). The array offers advantages such as spatial imaging, and enables capture of both intensity and precise photon arrival times across the photodiodes. In view of Stark, a PHOSITA would find is obvious to modify Yamashita to include a plurality of photodiodes in an array to enable spatial imaging and provide additional functionality as discussed in (¶¶91-100).
Claim 14 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed doping steps need not be formed by the process of “injecting dopants” and may be formed by any means for forming a doped region using any number of doping steps. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches ion implant techniques, related photodetectors, and antireflection structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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