CTNF 18/609,430 CTNF 102233 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 1-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1, where it is stated “forming a plurality of direct contact conductive patterns by etching the direct contact conductive layer using the plurality of bit line structures and the second mask pattern as etching masks”, the second mask pattern refers to layer 112 (see at least Fig. 9A) in the specification. However, as claimed, the second mask pattern acts as a mask for the plurality of direct contact conductive patterns 134 (see at least Fig. 10A) which are located least partially above the second mask pattern. A person of ordinary skill in the art before the effective filing date of the claimed invention would understand a mask layer to act as a mask for layers that are below it, not those above. The examiner acknowledges that the specification describes: “the second mask pattern 112 may function as an etching mask such that the second mask pattern 112 protects the element isolation film 116 and the plurality of active regions 118 located under the second mask pattern 112 from being removed.” (para. [0054]), however it is improper to import limitations from the specification into the claim (see MPEP 2111.01). Therefore, the description of the second mask pattern acting as a mask for the direct contact conductive patterns, as stated in claim 1, is not supported by the specification. For the purposes of examination, the claim limitation “forming a plurality of direct contact conductive patterns by etching the direct contact conductive layer using the plurality of bit line structures and the second mask pattern as etching masks” will be interpreted to mean that the bit-line structures act as a mask for the direct contact conductive patterns and the second mask pattern acts as a mask for the active regions and the isolation film. Claims 2-12 are rejected since they inherit the lack of support of the claims from which they depend. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 13-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Petz et al. (US 20180366386 A1) hereinafter referred to as “Petz386” . Regarding claim 13: Petz386 teaches a manufacturing method of a semiconductor device (para. [0002]), the method comprising: forming a target layer (Fig. 1, elements 102, 104; para. [0017]) on a substrate (Fig. 1, element 112); forming a mask pattern (Fig. 1, element 114) on the substrate including the target layer; and forming a resulting pattern (etch channels, Fig. 1, element 110) by etching the target layer using the mask pattern, wherein the mask pattern comprises, a first mask layer (Fig. 1 as annotated below, first-mask layer) containing an amorphous metal oxide (Magnesium Aluminum Oxide, para. [0044]); and an upper mask layer (Fig. 1 as annotated below, upper-mask layer) and a lower mask layer (Fig. 1 as annotated below, lower-mask layer) including an amorphous metal oxide or an amorphous insulating material that does not include metal (as claimed, the first, upper, and lower mask layers could include an amorphous metal oxide, this means that a single layer of amorphous metal oxide could be arbitrarily divided into sublayers and would anticipate the claim), the an upper mask layer and the lower mask layer covering upper and lower surfaces of the first mask layer, respectively (Fig. 1 as annotated below). PNG media_image1.png 443 1084 media_image1.png Greyscale Regarding claim 14: Petz386 teaches that the mask pattern further comprises a hard mask layer (See annotated Fig. 1 above, hard-mask layer) disposed under the lower mask layer (See annotated Fig. 1 above, lower-mask layer) and including metal (Since the claim language does not specify that the layers must be made of separate materials, a single hard mask containing an amorphous metal oxide can arbitrarily be divided into layers and anticipate the claim, in this case, a hard mask made of amorphous Magnesium Aluminum Oxide.) Regarding claim 15: Petz386 teaches that the target layer may be made of metal or a conductive metal compound (para. [0017]). Regarding claim 16: Petz386 teaches forming a mask pattern structure on the target layer (Fig. 1, element 116), wherein the resulting pattern is a portion of the target layer overlapping the mask pattern structure (in light of the specification, the resulting pattern is interpreted by the examiner to mean the areas removed in the target layer after etching, and the mask pattern structure is interpreted to mean materials deposited into the areas removed in the target layer after etching) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, and 7-9, and 17-20 is/are rejected under 35 U.S.C. 103, as best understood, as being unpatentable over Ahn et al. (US 20210124258 A1), hereinafter referred to as “Ahn258” in view of Park et al. (US 20140374809 A1) hereinafter referred to as “Park809” and Petz et al. (US 20180366386 A1), hereinafter referred to as “Petz386”. Regarding claims 1 and 17: Ahn258 teaches a manufacturing method of a semiconductor device (para. [0002]), the method comprising: preparing a substrate (Fig. 14A, element 110) including a plurality of active regions (Fig. 14A, element 118) defined by an element isolation film (Fig. 14A, element 116); forming a word line trench (Figs. 14B-14D, element 120T) extending in a first horizontal direction across the plurality of active regions in the substrate; forming a word line (Fig. 14C, element 120) within the word line trench; forming a second mask pattern (Fig. 15A, element 112)) defining a direct contact hole (Fig. 15A, element 134H) extending into the substrate on the substrate where the word line is formed (para. [0099]); forming a direct contact conductive layer (para. [0100]); forming a plurality of bit line structures (Fig. 16A, element 140), each including a bit line (Fig. 16A, element 147), the plurality of bit line structures being parallel to each other in the first horizontal direction and extending in a second horizontal direction orthogonal to the first horizontal direction on the second mask pattern and the direct contact conductive layer (Figs. 11A and 11B, para. [0070]); forming a plurality of direct contact conductive patterns (Fig. 16A, element 134) by etching the direct contact conductive layer using the plurality of bit line structures and the second mask pattern as etching masks (paras. [0100] and [0101]); forming a plurality of buried contacts (Fig. 17A element 170) and a plurality of landing pads (Fig. 20A, element 190) on the plurality of buried contacts, the plurality of buried contacts electrically connected to the plurality of active regions (active regions are connected to storage nodes through a path containing the buried contacts and the landing pads, implying that the buried contacts are electrically connected to the active regions, para. [0074]), and the plurality of landing pads filling a portion of a space between the plurality of bit line structures (Fig. 21A, landing pads 190, bit-lines 140); Ahn258 does not explicitly teach that the word line trenches are formed by removing a portion of the element isolation film and a portion of each of the plurality of active regions using a first mask pattern; Ahn258 also does not explicitly teach that the direct contact conductive layer includes a metal or a metal compound, or that forming a mold layer on the plurality of bit line structures and the plurality of landing pads; forming a plurality of mold openings by etching the mold layer using a third mask pattern; and forming a plurality of lower electrodes filling the plurality of mold openings. Park809 teaches forming a trench on a substrate by removing portions of the substrate and the isolation layer pattern (Figs. 30 and 31, first hard mask 310, substrate 300, isolation layer pattern 320, para. [0129]). Park 809 teaches that the direct contact conductive material includes a metal or a metal compound (“The barrier layer may be formed to include a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride, etc.”, para. [0138])) as a conductive material to fill the direct contact holes. Park809 additionally teaches that a mold layer may be disposed on the landing pads and etched to form third contact holes and forming electrodes within the contact holes (paras. [0153] and [154]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a trench on a substrate using a mask pattern, to use a material containing metal as a conductive material to fill the contact holes, and to form electrodes to act as capacitors in a memory device by forming and etching a mold layer, as these are practices widely used in the semiconductor manufacturing industry. This is simply combining prior art elements according to known methods to yield predictable results. Ahn258 and Park809 do not explicitly teach that at least one of the first mask pattern, the second mask pattern, and the third mask pattern has a stacked structure of a first mask layer and at least two second mask layers, the first mask layer including an amorphous metal oxide, and the at least two second mask layers including an amorphous metal oxide or an amorphous insulating material that does not include metal. Petz386 teaches that a hard mask may be made of amorphous Magnesium Aluminum Oxide which has beneficial effects due to a very high wet etch rate, being easily stripped during a wet etch after a dry etch is performed with a low risk of contamination (para. [0044]). Similar to the reasoning given in the rejection of claims 13-15, a single layer of amorphous metal oxide can be arbitrarily divided into three or more sub-layers (See annotated Fig. 1 above) and each sublayer would contain an amorphous metal oxide or an amorphous insulating material that does not include metal as claimed). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a mask containing amorphous metal oxide, as stated above, due to the high etch rate and low risk of contamination. A person of ordinary skill at a time before the effective filing date of the claimed invention would be motivated by the teaching in Petz386 to modify the mask material in Ahn258 to arrive at the claimed invention. Regarding claim 2: Petz386 teaches the at least two second mask layers comprise an upper mask layer (Fig.1 annotated above, upper-mask layer) covering an upper surface of the first mask layer and a lower mask layer (Fig.1 annotated above, lower-mask layer) covering a lower surface of the first mask layer. As claimed, the upper mask layer and the lower mask layer do not need to made of a different material than the first mask layer. Regarding claims 4 and 18: Petz386 teaches the first mask layer comprises a plurality of sub-mask layers (Fig.1 annotated above, first-mask sub-layer) spaced apart from each other in a vertical direction, and the at least two second mask layers further comprise an intermediate mask layer (Fig. 1 annotated above, intermediate mask layer) disposed between each of the plurality of sub-mask layers. (As claimed the plurality of sub-mask layers and the intermediate mask layers do not need to made of a different material than, the hard, first, upper or lower mask layer, in this case, amorphous Magnesium Aluminum Oxide, para. [0044].) Regarding claims 3, 5, 19, and 20: Petz386 teaches that the thickness of each of the upper mask layer and the lower mask layer is about 10% to about 30% of a thickness of the first mask layer. (“The hard mask layer may be formed in any suitable manner. In a particular embodiment, a multi-cathode sputtering tool may sputter MgO via one cathode while utilizing another cathode to sputter Aluminum Oxide, Silicon Dioxide, or Hafnium Oxide onto the wafer (or multiple other cathodes may each sputter one of Aluminum Oxide, Silicon Dioxide, or Hafnium Oxide)”, para. [46]). Petz386 also teaches that a thickness of each of the plurality of sub-mask layers is 20 Å or less, and a thickness of each of the at least two second mask layers is greater than 2 Å, and is about 10% to about 30% of a thickness of each of the plurality of sub-mask layers. (Sputtering or Physical Vapor Deposition (PVD) is a common semiconductor manufacturing method that can achieve any desired film thickness in the nanometer to micrometer range). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to achieve the desired ratio of the thickness of the first, upper, and lower mask layers and to achieve the desired thickness of 20 Å or less by using PVD methods. This is simply applying known methods to achieve predictable results. Regarding claim 7: Ahn258 does not explicitly teach that the first mask layer includes HfO 2 or ZrO 2 , and each of the at least two second mask layers include Al 2 O 3 . Petz386 teaches that a hard mask of Magnesium Aluminum Oxide may be alloyed with Hafnium Oxide and Aluminum Oxide to better control the etching rate of the hard mask (para. [0045]) and the optimal combination is approximately 50% Hafnium Oxide 25% Magnesium Aluminum Oxide and 25% Aluminum Oxide (para. [0045]). Since the hard mask layer is an alloy containing both Hafnium Oxide and Aluminum Oxide, the hard mask layer can be arbitrarily divided into a first mask layer and at least two second mask layers, where the first mask layer contains Hafnium Oxide and the at least two second layers contain Aluminum Oxide. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a mask containing the optimal composition as disclosed by Petz386 to modify the mask material in Ahn258 to arrive at the claimed invention. Regarding claim 8: Petz386 teaches at least one of the first mask pattern and the third mask pattern further comprises a hard mask layer (Fig. 1 annotated above, hard-mask layer) disposed under the first mask layer (Fig. 1 annotated above, first-mask layer) and the at least two second mask layers (at least upper-mask layer, lower-mask layer). Regarding claim 9: Petz386 teaches that the hard mask layer is a metal mask layer doped with metal (amorphous Magnesium Aluminum Oxide, para. [0044]). 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 20210124258 A1), hereinafter referred to as “Ahn258” in view of Park et al. (US 20140374809 A1) hereinafter referred to as “Park809” and Okabe et al. (US 20210280419 A1) hereinafter referred to as “Okabe419” . Regarding claim 6: Ahn258 and Park809 teach the limitations of claim 1 as described above, they do not explicitly teach the limitation of “at least one of the first mask pattern, the second mask pattern, and the third mask pattern having a stacked structure of a first mask layer and at least two second mask layers, the first mask layer including an amorphous metal oxide, and the at least two second mask layers including an amorphous metal oxide or an amorphous insulating material that does not include metal”. Additionally, they do not teach the limitation of “the at least first, second, or third mask pattern having the at least two second mask layers including a material having a crystallization temperature that is higher than a crystallization temperature of the first mask layer”. Okabe419 teaches a hard mask comprising two layers (Fig. 4, first hard mask 103, second hard mask 104) the first hard mask being an amorphous film containing tungsten (para. [0077]) and the second hard mask layer being an amorphous film containing zirconium or titanium (para. [0081]). Either the first hard mask layer or the second hard mask layer can be arbitrarily divided into two sub-layers of any desired thickness (see Fig. 1 annotated above) to be the “at least two second mask layers” as claimed, and since the first hard mask and second hard mask are comprised of different amorphous materials, it is inherent that they possess different crystallization temperatures. Okabe419 teaches that in pattern formation for a hard mask having the first hard mask and the second hard mask, the shape abnormality of the pattern can be sufficiently suppressed using the amorphous metal oxide masks. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the mask material in Ahn258 to include layers of amorphous metal oxide comprised of different amorphous materials with a reasonable expectation of success . 07-21-aia AIA Claim (s) 10-12 , is/are rejected under 35 U.S.C. 103, as being unpatentable over Ahn et al. (US 20210124258 A1), hereinafter referred to as “Ahn258” and Petz et al. (US 20180366386 A1), hereinafter referred to as “Petz386” in view of Guo et al. (US 20200066730 A1) hereinafter referred to as “Guo730” . Regarding claims 10-12: Ahn258 and Petz386 teach all the limitations of claim 1, as described above. However, they do not explicitly teach forming a cover insulating film pattern to be between the second mask pattern and a corresponding one of the plurality of bit line structures in a vertical direction, wherein a horizontal width of the cover insulating film pattern is less than a horizontal width of the second mask pattern, forming a conductive semiconductor pattern to be between the corresponding one of the plurality of bit line structures and the cover insulating film pattern in a vertical direction, wherein a horizontal width of the cover insulating film pattern and a horizontal width of the conductive semiconductor pattern are equal to each other, or forming an insulating spacer structure covering each of both sidewalls of each of the plurality of bit line structures, wherein a lower surface of the insulating spacer structure is at a vertical level lower than an upper surface of the cover insulating film pattern and in contact with the second mask pattern. Guo730 recognizes that “the rate of material (e.g., hard mask material) removal depends on the aspect ratio of the opening (e.g., trench) being formed, which is defined as the ratio of the depth of the opening to the width (e.g., diameter). Openings with relatively higher aspect ratios are etched more slowly than openings with relatively smaller aspect ratios”. The aspect ratio of the opening is therefore a result-effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the result-effective variable of the aspect ratio of the openings between bit-lines (see at least Fig. 10A, element 170H) by varying the horizontal width of the cover insulating film pattern and a horizontal width of the conductive semiconductor pattern as well as the height of the insulating spacer structure, in order to determine the optimum or workable ranges of the opening aspect ratio and arrive at the claimed invention (see MPEP 2144.05). Furthermore, the applicant has not presented persuasive evidence that the claimed horizontal width of the cover insulating film pattern and a horizontal width of the conductive semiconductor pattern as well as the height of the insulating spacer structure are for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions). Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure. Yang et al. (US 20220359525 A1) and Kim (US 20150041888 A1) teach using bit-lines as a mask to form openings in the active region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)270-0853. The examiner can normally be reached M-F 9:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT L STEWART/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898 Application/Control Number: 18/609,430 Page 2 Art Unit: 2898 Application/Control Number: 18/609,430 Page 3 Art Unit: 2898 Application/Control Number: 18/609,430 Page 4 Art Unit: 2898 Application/Control Number: 18/609,430 Page 5 Art Unit: 2898 Application/Control Number: 18/609,430 Page 6 Art Unit: 2898 Application/Control Number: 18/609,430 Page 7 Art Unit: 2898 Application/Control Number: 18/609,430 Page 8 Art Unit: 2898 Application/Control Number: 18/609,430 Page 9 Art Unit: 2898 Application/Control Number: 18/609,430 Page 10 Art Unit: 2898 Application/Control Number: 18/609,430 Page 11 Art Unit: 2898 Application/Control Number: 18/609,430 Page 12 Art Unit: 2898 Application/Control Number: 18/609,430 Page 13 Art Unit: 2898
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