DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on June 24, 2026 is acknowledged.
Claims 9-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 24, 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, 9, 16-20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Cho et al (U.S. 2018/0286790).
Regarding claim 1. Cho et al discloses a package substrate (FIG. 11D, item 100) comprising:
a core dielectric (FIG. 11D, item 111a) that includes a first surface ([0077]), a second surface ([0077]), and a first cavity (FIG. 11D, item 111Ha, [0070]) through the core dielectric (FIG. 11D, item 111a) from the first surface ([0077]) to the second surface ([0077]);
a first metallization structure (FIG. 11D, item 112a1) on the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), the first metallization structure (FIG. 11D, item 112a1) including a first plurality of dielectric layers (FIG. 11D, items 111b,111d) with first conductive traces (FIG. 11D, item 112b,112d) and first conductive vias (FIG. 11D, item 113b,113d) disposed therein;
a second metallization structure (FIG. 11D, item 112a2) on the second surface ([0077]) of the core dielectric (FIG. 11D, item 111a) including a second plurality of dielectric layers (FIG. 11D, item 111c, 111e) with second conductive traces (FIG. 11D, item 112c, 112e) and second conductive vias (FIG. 11D, item 113c, 113e) disposed therein; and
a first embedded component (FIG. 11D, item 120) disposed in the first cavity (FIG. 11D, item 110Ha) and through at least the core dielectric (FIG. 11D, item 111a), one of the first plurality of dielectric layers (FIG. 11D, item 111b) immediately adjacent the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), and one of the second plurality of dielectric layers (FIG. 11D, item 111c) immediately adjacent the second surface ([0077]) of the core dielectric (FIG. 11D, item 111a).
Regarding claim 2. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses wherein: the first embedded component (FIG. 11D, item 120) is disposed through a first number of dielectric layers (FIG. 11D, item 111b, 111d) of the first plurality of dielectric layers (FIG. 11D, item 111b, 111d) and through a second number (FIG. 11D, item 111c, 111e) of dielectric layers of the second plurality of dielectric layers (FIG. 11D, item 111c, 111e), and
the first number (FIG. 11D, item 111b, 111d) equals ([0077]) the second number (FIG. 11D, item 111c, 111e).
Regarding claim 3. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses further comprising:
a second embedded component (FIG. 11D, item 125) disposed in a second cavity (FIG. 11D, item 110Hb) of the core dielectric (FIG. 11D, item 111a) and through at least the core dielectric (FIG. 11D, item 111a), the one (FIG. 11D, item 111b, 111d) of the first plurality of dielectric layers (FIG. 11D, item 111b, 111d) immediately adjacent the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), and the one (FIG. 11D, item 111c, 111e) of the second plurality of dielectric layers (FIG. 11D, item 111c, 111e) immediately adjacent the second surface ([0077]) of the core dielectric(FIG. 11D, item 111a),
wherein a first thickness ([0071]) of the first embedded component and a second thickness ([0071]) of the second embedded component are different ([0071], i.e. Particularly, a plurality of passive components may have different thicknesses, and a thickness difference between the plurality of passive components and the semiconductor chips may be significant).
Regarding claim 4. Cho et al discloses all the limitations of the package substrate of claim 3 above.
Cho et al further discloses wherein: the first embedded component (FIG. 11D, item 120) includes first conductive terminals (FIG. 11D, item 122), the second embedded component (FIG. 11D, item 125) includes second conductive terminals ([0070]), and the first conductive terminals (FIG. 11D, item 122) and the second conductive terminals ([0070], i.e. the second passive components 125 may be electrically connected to the connection pads 122 of the semiconductor chip 120 through the redistribution layers 142 of the second connection member 140.) are disposed at a same side of the core dielectric (FIG. 11D, item 111a) or at different sides of the core dielectric.
Regarding claim 5. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses wherein the first embedded component (FIG. 11D, items 120) comprises: a chip ([0070], i.e. a semiconductor chip 120), or the chip and a dummy structure stacked one over the other.
Regarding claim 6. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses further comprising: a third embedded component (FIG. 11D, items 128) disposed in a third cavity (FIG. 11D, items 111aH) of the core dielectric (FIG. 11D, item 111a), without passing through the one of the first plurality of dielectric layers (FIG. 11D, items 111b,111d) immediately adjacent the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), and without passing through the one of the second plurality of dielectric layers (FIG. 11D, items 111c,111e) immediately adjacent the second surface ([0077]) of the core dielectric (FIG. 11D, item 111a).
Regarding claim 8. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses wherein the first embedded component (FIG. 11D, item 120) comprises: a capacitive device; an inductive device; a resistive device; an active device ([0084]); or any combination thereof.
Regarding claim 9. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses wherein: the core dielectric (FIG. 11D, item 111a) comprises resin ([0080]) or fiber-reinforced composite resin ([0080]), and the first plurality of dielectric layers (FIG. 11D, items 111b,111d) and the second plurality of dielectric layers (FIG. 11D, items 111c,111e) are formed based on build-up dielectric films ([0080]).
Regarding claim 16. Cho et al discloses an electronic device (FIG. 1 and 2), comprising: a package substrate (FIG. 11D, item 100) that includes:
a core dielectric (FIG. 11D, item 111a) that includes a first surface ([0077]), a second surface ([0077]), and a first cavity (FIG. 11D, item 111Ha, [0070]) through the core dielectric (FIG. 11D, item 111a) from the first surface ([0077]) to the second surface ([0077]);
a first metallization structure (FIG. 11D, item 112a1) on the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), the first metallization structure (FIG. 11D, item 112a1) including a first plurality of dielectric layers (FIG. 11D, items 111b,111d) with first conductive traces (FIG. 11D, item 112b,112d) and first conductive vias (FIG. 11D, item 113b,113d) disposed therein;
a second metallization structure (FIG. 11D, item 112a2) on the second surface ([0077]) of the core dielectric (FIG. 11D, item 111a) including a second plurality of dielectric layers (FIG. 11D, item 111c, 111e) with second conductive traces (FIG. 11D, item 112c, 112e) and second conductive vias (FIG. 11D, item 113c, 113e) disposed therein; and
a first embedded component (FIG. 11D, item 120) disposed in the first cavity (FIG. 11D, item 110Ha) and through at least the core dielectric (FIG. 11D, item 111a), one of the first plurality of dielectric layers (FIG. 11D, item 111b) immediately adjacent the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), and one of the second plurality of dielectric layers (FIG. 11D, item 111c) immediately adjacent the second surface ([0077]) of the core dielectric (FIG. 11D, item 111a).
Regarding claim 17. Cho et al discloses all the limitations of the electronic device (FIG. 1 and 2) of claim 16 above.
Cho et al further discloses wherein the package substrate (FIG. 11D, item 100) further comprises:
a second embedded component (FIG. 11D, item 125) disposed in a second cavity (FIG. 11D, item 110Hb) of the core dielectric (FIG. 11D, item 111a) and through at least the core dielectric (FIG. 11D, item 111a), the one (FIG. 11D, item 111b, 111d) of the first plurality of dielectric layers (FIG. 11D, item 111b, 111d) immediately adjacent the first surface ([0077]) of the core dielectric (FIG. 11D, item 111a), and the one (FIG. 11D, item 111c, 111e) of the second plurality of dielectric layers (FIG. 11D, item 111c, 111e) immediately adjacent the second surface ([0077]) of the core dielectric(FIG. 11D, item 111a),
wherein a first thickness ([0071]) of the first embedded component and a second thickness ([0071]) of the second embedded component are different ([0071], i.e. Particularly, a plurality of passive components may have different thicknesses, and a thickness difference between the plurality of passive components and the semiconductor chips may be significant).
Regarding claim 18. Cho et al discloses all the limitations of the electronic device (FIG. 1 and 2) of claim 16 above.
Cho et al further discloses wherein the first embedded component (FIG. 11D, items 120) comprises: a chip ([0070], i.e. a semiconductor chip 120), or the chip and a dummy structure stacked one over the other.
Regarding claim 19. Cho et al discloses all the limitations of the electronic device of claim 16 above.
Cho et al further discloses wherein: the core dielectric (FIG. 11D, item 111a) comprises resin ([0080]) or fiber-reinforced composite resin ([0080]), and the first plurality of dielectric layers (FIG. 11D, items 111b,111d) and the second plurality of dielectric layers (FIG. 11D, items 111c,111e) are formed based on build-up dielectric films ([0080]).
Regarding claim 20. Cho et al discloses all the limitations of the electronic device (FIG. 1 and 2) of claim 16 above.
Cho et al further discloses wherein the electronic device (FIG. 11D, item 100) comprises a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle ([0036]-[0043]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (U.S. 2018/0286790) as applied to claim 1 above, and further in view of Sakai et al (U.S. 2016/0316566).
Regarding claim 7. Cho et al discloses all the limitations of the package substrate of claim 1 above.
Cho et al further discloses wherein: the first plurality of dielectric layers (FIG. 11D, items 111b,111d), and the second plurality of dielectric layers (FIG. 11D, items 111c,111e).
Cho et al fails to explicitly disclose:
wherein: the first plurality of dielectric layers includes six or more dielectric layers, and the second plurality of dielectric layers includes six or more dielectric layers.
However, Sakai et al teaches wherein: the first plurality of dielectric layers (FIG. 18, items 12, 21, 25 above item 12a) includes six (FIG. 18, items 12, 21 and 25; [0033], three first insulating resin layers 12, [0036], i.e. two second insulating resin layers 21, [0038] i.e. A solder resist layer 25) or more dielectric layers (FIG. 18, items 12, 21, 25 above item 12a), and the second plurality of dielectric layers (FIG. 18, items 12, 21, 25 below item 12a) includes six (FIG. 18, items 12, 21 and 25; [0033], [0036], [0038]) or more dielectric layers (FIG. 18, items 12, 21, 25 below item 12a).
Since Cho et al and Sakai et al teach package core substrate with through-holes, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the package substrate as disclosed to modify Cho et al with the teachings of wherein the first plurality of dielectric layers includes six or more dielectric layers, and the second plurality of dielectric layers includes six or more dielectric layers as disclosed by Sakai et al. The use multiple layers in Sakai et al provides for overall rigidity of the wiring board with a built-in electronic component can be improved (Sakai et al, [0084]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsu et al (U.S. 2009/0085192) Packaging Substrate Structure Having Semiconductor Chip Embedded Therein And Fabricating Method Thereof.
Hsu et al (U.S. 2022/0285282) Substrate Structure and Semiconductor Structure.
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/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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