DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-3, 6-7, 9,10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855) in view of Chou et al (US 20210296312) and the following arguments.
Regarding Claim 1, Ng teaches A method of forming a semiconductor device, the method comprising (1000, Fig. 3, para [0092]): forming a first fin (118, Fig. 1, para [0018]), a second fin (120, Fig. 1, para [0018]) that protrude above a substrate and extend parallel to each other (118 & 120, Fig. 1, para [0018]); forming a gate structure over the first fin (126, Fig. 2E-2, para [0039]), the second fin (126, Fig. 2E-2, para [0039]); forming gate spacers ((132, Fig. 2F-3, along opposing sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer (138, Fig. 2E-1, para [0039]) over the first fin (118, Fig. 1, para [0018]), the second fin (120, Fig. 1, para [0018]) around the gate structure (126, Fig. 2E-2, para [0039]); forming, in the gate structure (126, Fig. 2E-2, para [0039]), a first dielectric plug (174, Fig. 2K-1 & 2K-2, para [0087]) and a second dielectric plug (174, Fig. 2K-1 & 2K-2, para [0087]) that separate the gate structure into a plurality of segments (shown in figure below); forming a patterned mask layer over the ILD layer (140, Fig. 2F-1, para [0060]), wherein a first opening of the patterned mask layer (142, Fig. 2F-1, para [0055]) exposes a first segment of the gate structure (412, Fig. 4C, para [0100]); performing a first etching process using the patterned mask layer as an etching mask (140, Fig. 2F-1, para [0060]), wherein the first etching process recesses the first segment of the gate structure and forms a recess between the gate spacers (no reference number, Fig. 2F-3, para [0108] & [0054]; based on the etching step cycles there exists a point where there is a recess of the gate structure between the gate spacers that does not reach the substrate yet); after performing the first etching process, performing a second etching process different from the first etching process to deepen the recess (144, Fig. 2F-2, para [0109] & [0054]), wherein after the second etching process is finished, the recess extends into the substrate (144B, Fig. 2F-2, para [0054]); and after performing the second etching process (144, Fig. 2F-2, para [0109]), forming a dielectric structure in the recess (146, Fig. 2G-2, para [0059]).
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Ng does not explicitly teach wherein forming a patterned mask layer with an opening the first segment of the gate structure disposed between the first dielectric plug and the second dielectric plug.
However, Ng does teach dielectric gate-cuts/plugs that do later bound the etched gate (as shown in Fig. 2K-2), which substantially match the instant case. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to reorder the process steps in order to form the dielectric plugs before the two step gate etch process for the advantage of favorable etching selectivity leading to more reliable etching outcomes (see para [0090]).
Ng does not explicitly teach and a third fin, wherein the third fin is between the first fin and the second fin. wherein the first dielectric plug is formed between the first fin and the third fin, and the second dielectric plug is formed between the third fin and the second fin.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Chou teaches a semiconductor device with a plurality of parallel fins. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to add a third fin and accompanying regions to Ng based on the teachings of Chou for the advantage of furthering device capability while still being efficient with device size.
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Regarding Claim 2, Ng teaches The method of claim 1 (1000, Fig. 3, para [0092]), wherein in a top view, there is a lateral offset between a first center axis of the first opening (144, Fig. 2F-2, para [0109] & [0054]) and a longitudinal center axis of the gate structure (shown in figure below), wherein the first center axis of the first opening (144, Fig. 2F-2, para [0109] & [0054]) and the longitudinal center axis of the gate structure (shown in figure below) extend in parallel (shown in figure below).
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Regarding Claim 3, The method of claim 2 (1000, Fig. 3, para [0092]),
Ng does not explicitly teach wherein the lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Chou teaches a first and second fin region that is laterally offset from an isolation region by a non-zero distance (Chou, para [0049]). Chou further teaches the rationale in implementing a laterally offset isolation region (Chou, para [0049]).
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to routinely optimize the lateral offset in Ng as taught by Chou for the purpose of optimizing semiconductor IC dimensions (Ng, para [0002]) and an effective isolation structure between fin structures.
Regarding Claim 6, Ng teaches The method of claim 1 (1000, Fig. 3, para [0092]), wherein an etching selectivity of the second etching process (144, Fig. 2F-2, para [0109] & [0054]),
Ng does not explicitly teach calculated as a ratio between a first etch rate of the substrate and a second etch rate of the gate spacers, is between about 0.2 and about 5.
However, teaches that the gate spacers can be silicon oxide and the material of the substrate can be silicon, which are the exact same as in the instant case. Ng also further teaches a bias voltage that encompasses the later claimed applicant’s range. Therefore, the same materials treated the same way constitute that the etch rate range defined as about 0.2 and about 5 are an inherent property.
Regarding Claim 7, Ng teaches The method of claim 6 (1000, Fig. 3, para [0092]), wherein the second etching process is an plasma etching process (1018, Fig. 3, para [0047]), wherein the method further comprises setting an amplitude of a bias voltage of the anisotropic plasma etching process (1018, Fig. 3, para [0108]).
Ng does not explicitly teach wherein the plasma etching process is an anisotropic etching process
However, Ng does disclose that the etching process may be performed in a plasma etch chamber (para [0101]) and uses an anisotropic etching process for other etch processes, implying that it is already known. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use an anisotropic etching process to deepen the recess for the well known advantage of obtaining a higher aspect ratio as compared to other dry plasma etching methods.
Ng does not explicitly teach between about 500 V and about 1200 V.
However, Ng discloses a range of 350 V to about 2100 V (para [0108]) which encompasses the applicant’s claimed range and thus constitutes a prima facie case of obviousness (MPEP 2144.05).
Regarding Claim 9, Ng and Chou teach The method of claim 1 (1000, Fig. 3, para [0092]), wherein the gate structure is a dummy gate structure (126, Fig. 2E-2, para [0039]), wherein the method further comprises, after filling the recess (150, Fig. 2G-2, para [0059]): removing the patterned mask layer (140, Fig. 2G-1, para [0060]); and replacing a second segment of the dummy gate structure (152, Fig. 2H-3, para [0062]) and a third segment of the dummy gate structure (152, Fig. 2H-3, para [0062]) with a first replacement gate structure (160, Fig. 2I-1, para [0072]) and a second replacement gate structure (160, Fig. 2I-1, para [0072]), respectively, wherein the second segment of the dummy gate structure overlies the first fin, and the third segment of the dummy gate structure overlies the second fin (shown in fig below).
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Regarding Claim 10, Ng teaches The method of claim 1 (1000, Fig. 3, para [0092]), wherein the dielectric structure has a multi-layer structure (146, Fig. 2G-2, para [0059]), wherein forming the dielectric structure comprises: forming a first dielectric material along sidewalls and a bottom of the recess (148, Fig. 2G-2, para [0059]); and after forming the first dielectric material, forming a second dielectric material (150, Fig. 2G-2, para [0060]) different from the first dielectric material (para [0060]) in the recess over the first dielectric material (shown in fig below).
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Regarding Claim 12, Ng teaches The method of claim 1, further comprising, after performing the first etching process (144B, Fig. 2F-2, para [0054]) and before performing the second etching process (144B, Fig. 2F-2, para [0054]).
Ng does not explicitly teach wherein forming a passivation layer along sidewalls and a bottom of the recess; and after forming the passivation layer, removing the passivation layer from the bottom of the recess.
However, the use of a passivation layer, and its advantages, for etching in semiconductor devices is well known in the art as of the time of the effective filing date. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to include a passivation step in the etching process (para[0101]) for the advantage of creating a trench with a higher aspect ratio.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855), Chou et al (US 20210296312), and the previous arguments as applied to claim 1-3, 6-7, 9,10, 12 above, and further in view of Xie et al (US 20170243790).
Regarding Claim 4, Ng teaches The method of claim 2 (1000, Fig. 3, para [0092]), wherein forming the patterned mask layer comprises: forming a hard mask layer (140, Fig. 2F-1, para [0060]) over the ILD layer (138, Fig. 2E-1, para [0039]); forming a photoresist layer (408, Fig. 2A, para [0099]) over the hard mask layer (402, Fig. 4A, para [0099]); forming a second opening in the photoresist layer to form a patterned photoresist layer, wherein in the top view, a second center axis of the second opening is laterally shifted from the longitudinal center axis of the gate structure by a predetermined amount; and patterning the hard mask layer using the patterned photoresist layer to form the patterned mask layer, wherein the second opening of the patterned photoresist layer corresponds to the first opening of the patterned mask layer due to the patterning of the hard mask layer.
Ng does not explicitly teach wherein forming a second opening in the photoresist layer to form a patterned photoresist layer, wherein in the top view, a second center axis of the second opening is laterally shifted from the longitudinal center axis of the gate structure by a predetermined amount; and patterning the hard mask layer using the patterned photoresist layer to form the patterned mask layer, wherein the second opening of the patterned photoresist layer corresponds to the first opening of the patterned mask layer due to the patterning of the hard mask layer.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Xie teaches a photoresist opening that is in the top view, is laterally shifted from the longitudinal center axis of the gate structure by a predetermined amount (figure shown below).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to form a second opening in the photoresist layer of Ng that is laterally shifted from longitudinal center axis of the gate structure by a predetermined amount, for the advantage of improving manufacturing yield by designing a process that can account for imperfect nano-misalignments. Ng further teaches a patterning of the hard mask layer due to the patterning of the photoresist layer (1018, Fig. 3 & Fig. 4A-4D, para [0101]). Which combines to meet all limitations of the claim above.
Regarding Claim 5, Ng and Chou The method of claim 2 (1000, Fig. 3, para [0092]), wherein after the first etching process (discussed in claim 1), wherein after the second etching process and before filling the recess (144, Fig. 2F-3, para [0053]), the first sidewall and the second opposing sidewall of the gate spacers are exposed to the recess (132, Fig. 2F-3, para [0056[).
Ng does not explicitly teach a first sidewall of the gate spacers facing the gate structure is exposed to the recess, and a second opposing sidewall of the gate spacers facing the gate structure is covered by a remaining portion of the gate structure.
However, a first sidewall of the gate spacers facing the gate structure is exposed to the recess, and a second opposing sidewall of the gate spacers facing the gate structure is covered by a remaining portion of the gate structure would be a natural consequence of for the combination of Ng and Xie as shown above in claim 4. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to form a second opening in the photoresist layer of Ng that is laterally shifted from longitudinal center axis of the gate structure by a predetermined amount, for the advantage of improving manufacturing yield by designing a process that can account for imperfect nano-misalignments. And since the misalignment effects the mask pattern and subsequent gate etching orientation, a misalignment enough to cause a first sidewall of the gate spacers facing the gate structure is exposed to the recess, and a second opposing sidewall of the gate spacers facing the gate structure is covered by a remaining portion of the gate structure is an artifact of the described process.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855), Chou et al (US 20210296312), and the previous arguments as applied to claim 1-3, 6-7, 9,10, 12 above, and further in view of Chang (US 20210343578).
Regarding Claim 11, Ng and Chou teach The method of claim 1 (1000, Fig. 3, para [0092]), further comprising, after forming the dielectric structure (146, Fig. 2G-2, para [0059])
Ng does not explicitly teach wherein forming a front-side interconnect structure over and electrically coupled to the gate structure; bonding the front-side interconnect structure to a carrier; after the bonding, performing a backside thinning process to remove the substrate and portions of the first fin, the second fin, and the third fin; after the backside thinning process, forming a backside via that extends through the third fin and electrically coupled to a source/drain region adjacent to the gate structure; and after forming the backside via, forming a backside interconnect structure that is electrically coupled to the backside via.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Chang teaches wherein forming a front-side interconnect structure (Chang, 250, Fig. 16, para [0059]) over and electrically coupled to the gate structure (Chang, 255 & 256, Fig. 16, para [0061]); bonding the front-side interconnect structure to a carrier (Chang, 260, Fig. 17, para [0062]); after the bonding, performing a backside thinning process to remove the substrate (Chang, 110, Fig. 18, para [0017]) and portions of the first fin, the second fin, and the third fin (shown below; but related to Chang, 130, Fig. 19, para [0023])); after the backside thinning process, forming a backside via (Chang, 292, Fig. 25, para [0073]) that extends through the third fin (Ng and Chou, figure used for claim 1 rejection) and electrically coupled to a source/drain region (Chang, 190S/D, Fig. 25, para [0044]) adjacent to the gate structure (Chang, 220, Fig. 25, para [0056]); and after forming the backside via (Chang, 292, Fig. 25, para [0073]), forming a backside interconnect structure that is electrically coupled to the backside via (300, Fig. 25, para [0074]).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to include front-side and back side interconnect structure to the semiconductor device of Ng and Chou in view of Chang for the advantage of being able to efficiently connect more and/or different circuit elements to the device.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855), Chou et al (US 20210296312), and the previous arguments as applied to claim 1-3, 6-7, 9,10, 12 above, and further in view of Kiehlbauch (US 20140357086).
Regarding Claim 8, Ng teaches The method of claim 6 (1000, Fig. 3, para [0092]), wherein after the second etching process (1018, Fig. 3, para [0108]), a lower portion of the recess extends into the substrate (144B, Fig. 2F-2, para [0054]).
Ng does not explicitly teach wherein sidewalls of the lower portion of the recess have a linear profile and intersect to form a V-shape.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Kiehlbauch teaches a V-shaped substrate opening profile (Fig. 14). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to shape the lower substrate recess portion of Ng into a V-shape according to the teachings of Kiehlbauch for the well known advantage of filling a tapered recess with dielectric material more efficiently.
Claim(s) 13, 15, 17-18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855) and in view of the following arguments.
Regarding Claim 13, Ng teaches A method of forming a semiconductor device, the method comprising (1000, Fig. 3, para [0092]): forming a gate structure (126, Fig. 2F-2, para [0039]) over a fin that protrudes above a substrate (118 & 120, Fig. 1, para [0018]); forming an interlayer dielectric (ILD) layer (138, Fig. 2E-1, para [0039]) over the fin around the gate structure; forming a first dielectric plug (174, Fig. 2K-1 & 2K-2, para [0087]) and a second dielectric plug (174, Fig. 2K-1 & 2K-2, para [0087]) in the gate structure on opposing sides of the fin, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments that are separated from each other (shown in figure below); forming a patterned mask layer over the ILD layer (140, Fig. 2F-1, para [0060]); etching, using the patterned mask layer as an etching mask (no ref number, Fig. 4A-4D, para [0101]), the segment of the gate structure to form a recess in the gate structure (144, Fig. 2F-2, para [0109] & [0054]); extending the recess into the fin (144B, Fig. 2F-2, para [0109] & [0054]),; and after extending the recess, filling the recess with a dielectric material (146, Fig. 2G-2, para [0059]).
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Ng does not explicitly teach wherein an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug; etching
However, Ng does teach dielectric gate-cuts/plugs that do later bound the etched gate (as shown in Fig. 2K-2), which substantially match the instant case. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to reorder the process steps in order to form the dielectric plugs before the two step gate etch process for the advantage of favorable etching selectivity leading to more reliable etching outcomes (see para [0090]).
Ng does not explicitly teach wherein extending the recess comprises performing an anisotropic etching process to deepen the recess.
However, Ng does disclose that the etching process may be performed in a plasma etch chamber (para [0101]) and uses an anisotropic etching process for other etch processes, implying that it is already known. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use an anisotropic etching process to deepen the recess for the well known advantage of obtaining a higher aspect ratio as compared to other dry plasma etching methods.
Regarding Claim 15, Ng teaches The method of claim 13 (1000, Fig. 3, para [0092]), wherein an etching selectivity of the anisotropic etching process (1000, Fig. 3, para [0101]) is between about 0.2 and about 5, wherein the etching selectivity is computed as a ratio between a first etch rate of the substrate and a second etch rate of gate spacers of the gate structure.
Ng does not explicitly teach wherein the etching process is between about 0.2 and about 5, wherein the etching selectivity is computed as a ratio between a first etch rate of the substrate and a second etch rate of gate spacers of the gate structure.
However, Ng teaches that the gate spacers can be silicon oxide and the material of the substrate can be silicon, which are the exact same as in the instant case. Ng also further teaches a bias voltage that encompasses the later claimed applicant’s range. Therefore, the same materials treated the same way constitute that the etch rate range defined as about 0.2 and about 5 are an inherent property.
Regarding Claim 16, Ng teaches The method of claim 13 (1000, Fig. 3, para [0092]), wherein extending the recess comprises performing a plurality of etching cycles using the patterned mask layer as the etching mask (140, Fig. 2F-1, para [0060]), wherein each of the plurality of etching cycles (1000, Fig. 3, para [0101]) is performed by: anisotropic etching process to deepen the recess (144B, Fig. 2F-2, para [0109]).
Ng does not explicitly teach wherein the etching process: lining sidewalls and a bottom of the recess with a passivation layer; after the lining, removing the passivation layer from the bottom of the recess; and after removing the passivation layer from the bottom of the recess, performing the anisotropic etching process to deepen the recess.
However, the use of a passivation layer, and its advantages, for etching in semiconductor devices is well known in the art as of the time of the effective filing date. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to include a passivation step in the etching process (para[0101]) for the advantage of creating a trench with a higher aspect ratio.
Regarding Claim 17, Ng teaches The method of claim 13 (1000, Fig. 3, para [0092]), wherein forming the patterned mask layer (140, Fig. 2F-1, para [0060]) comprises forming the opening of the patterned mask layer (142, Fig. 2F-1, para [0060]) to be laterally shifted from a longitudinal center axis of the gate structure by a predetermined distance (shown in figure below).
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Regarding Claim 18, Ng teaches A method of forming a semiconductor device (1000, Fig. 3, para [0092]), the method comprising: forming a gate structure (126, Fig. 2F-2, para [0039]) over a fin that protrudes above a substrate (118 & 120, Fig. 1, para [0018]); forming an interlayer dielectric (ILD) layer (138, Fig. 2E-1, para [0039]) over the fin around the gate structure; forming a first dielectric plug (174, Fig. 2K-1 & 2K-2, para [0087]) and a second dielectric plug in the gate structure on opposing sides of the fin (174, Fig. 2K-1 & 2K-2, para [0087]), wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments (shown in figure below); forming a patterned mask layer over the ILD layer (140, Fig. 2F-1, para [0060]), wherein the opening of the patterned mask layer is formed to be laterally shifted from the segment of the gate structure by a predetermined distance (shown in figure below), wherein in a top view, there is a lateral offset between a longitudinal center axis of the gate structure and a center axis of the opening (shown in figure below); etching, using the patterned mask layer as an etching mask (no ref number, Fig. 4A-4D, para [0101]), the segment of the gate structure to form a recess in the gate structure (144, Fig. 2F-2, para [0109] & [0054]); extending the recess into the fin (144B, Fig. 2F-2, para [0109] & [0054]), where extending the recess comprises performing an etching process to deepen the recess (no reference number, Fig. 3, para [0101]); and after extending the recess, filling the recess with a dielectric material (146, Fig. 2G-2, para [0059]).
Ng does not explicitly teach wherein an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug.
However, Ng does teach dielectric gate-cuts/plugs that do later bound the etched gate (as shown in Fig. 2K-2), which substantially match the instant case. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to reorder the process steps in order to form the dielectric plugs before the two-step gate etch process for the advantage of favorable etching selectivity leading to more reliable etching outcomes (see para [0090]).
Ng does not explicitly teach wherein where extending the recess comprises performing an anisotropic etching process to deepen the recess.
However, Ng does disclose that the etching process may be performed in a plasma etch chamber (para [0101]) and uses an anisotropic etching process for other etch processes, implying that it is already known. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to use an anisotropic etching process to deepen the recess for the well known advantage of obtaining a higher aspect ratio as compared to other dry plasma etching methods.
Regarding Claim 20, Ng teaches The method of claim 18 (1000, Fig. 3, para [0092]), wherein the anisotropic etching process (discussed earlier in claim 18) is an anisotropic plasma etching process (1018, Fig. 3, para [0101]), wherein an etching selectivity of the anisotropic etching process is between about 0.2 and about 5 (discussed in claim 15), wherein the etching selectivity is calculated as a ratio between an etch rate of the substrate and an etch rate of gate spacers of the gate structure (discussed in claim 15).
Claim(s) 14, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al (US 20210183855) and the previous arguments as applied to claim13, 15, 17-18, 20 above, and further in view of Kiehlbauch (US 20140357086).
Regarding Claim 14, Ng teaches The method of claim 13 (1000, Fig. 3, para [0092]), wherein after extending the recess (144B, Fig. 2F-2, para [0056]).
Ng does not explicitly teach wherein a lower portion of the recess has slanted linear sidewalls, wherein a distance between the slanted linear sidewalls decreases as the recess extends toward the fin.
However, in an analogous field where a person of ordinary skill in the art would have a reasonable expectation of success, Kiehlbauch teaches a V-shaped substrate opening profile (Fig. 14) wherein a distance between the slanted linear sidewalls decreases as the recess extends toward the fin. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to shape the lower substrate recess portion of Ng into a V-shape according to the teachings of Kiehlbauch for the well known advantage of filling a tapered recess with dielectric material more efficiently.
Regarding Claim 19, Ng and Kiehlbauch teaches The method of claim 18 (1000, Fig. 3, para [0092]), wherein after extending the recess (144B, Fig. 2F-2, para [0056]) and before filling the recess (146, Fig. 2G-2, para [0059]), an upper portion of the recess disposed between gate spacers of the gate structure has a uniform width (shown in figure below), wherein a lower portion of the recess (144B, Fig. 2F-2, para [0056]) disposed between the upper portion of the recess (shown in figure below) and the substrate has slanted linear sidewalls (Kiehlbauch, Fig. 14, para [0044]), and a width of the lower portion of the recess decreases continuously as the lower portion of the recess extends toward the substrate (shown in figure below).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chapter 5: Polyimides for Electronic Applications
Used to show that the advantages of passivation layers are well known in the art
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/ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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