Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-14, 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yasukawa et al (hereinafter Yasukawa, US20250096087A1).
In regards to independent claim 1, Yasukawa teaches an integrated device comprising:
a die substrate (100);
a die interconnection portion coupled to the die substrate, wherein the die interconnection portion comprises (190+180):
at least one die dielectric layer (180); and
a plurality of die interconnects (190),
wherein the die interconnection portion comprises:
an inner die interconnection portion (left portion on Fig 7); and
a periphery die interconnection portion, wherein the periphery die interconnect portion is free of the plurality of die interconnects (right portion of Fig. 7);
a plurality of pad interconnects coupled to the die interconnection portion (Fig. 7 390);
a plurality of metallization interconnects coupled to the plurality of pad interconnects, wherein at least one metallization interconnect from the plurality of metallization interconnects, vertically overlaps with the periphery die interconnection portion (UBM 400, Fig. 7), and
a plurality of pillar interconnects coupled to the plurality of metallization interconnects (490).
In regards to dependent claim 2, Yasukawa teaches the integrated device of claim 1, wherein the plurality of pillar interconnects comprise:
a first pillar interconnect that vertically overlaps with the periphery die interconnection portion; and a second pillar interconnect that vertically overlaps with the inner die interconnection portion (Fig. 7).
In regards to dependent claim 3, Yasukawa teaches the integrated device of claim 2, wherein the first pillar interconnect does not vertically overlap with the plurality of die interconnects (Fig. 7).
In regards to dependent claim 4, Yasukawa teaches the integrated device of claim 2,
wherein the integrated device comprises: an inner region; and a periphery region,
wherein the inner die interconnection portion is part of the inner region of the integrated device, and wherein the periphery die interconnection portion is part of the periphery region of the integrated device (fig. 7 left side vs right side).
In regards to dependent claim 7, Yasukawa teaches the integrated device of claim 4,
wherein the die substrate includes an active region comprising a plurality of logic cells,
wherein the active region is located in the inner region of the integrated device, and
wherein the periphery region is free of any logic cells (Fig. 7).
In regards to dependent claim 8, Yasukawa teaches the integrated device of claim 7, wherein at least one pillar interconnect does not vertically overlap with the active region (Fig. 7)..
In regards to dependent claim 9, Yasukawa teaches the integrated device of claim 1, further comprising a seed layer that is part of the plurality of metallization interconnects ([0103}.
In regards to dependent claim 10, Yasukawa teaches the integrated device of claim 1, further comprising a plurality of solder interconnects coupled to the plurality of pillar interconnects (490, Fig. 7).
In regards to independent claim 11, Yasukawa teaches an integrated device comprising:
a die substrate (100);
a die interconnection portion coupled to the die substrate, wherein the die interconnection portion comprises (180, 190):
at least one die dielectric layer (180); and
a plurality of die interconnects (100, 190),
a plurality of pad interconnects coupled to the die interconnection portion (190);
an encapsulation layer coupled to (i) a side surface of the die substrate and (ii) a side surface of the die interconnection portion (170, Fig. 7);
a plurality of metallization interconnects coupled to the plurality of pad interconnects, wherein at least one metallization interconnect from the plurality of metallization interconnect vertically overlaps with the encapsulation layer (220, Fig. 7), and
a plurality of pillar interconnects coupled to the plurality of metallization interconnects (490).
In regards to dependent claim 12, Yasukawa teaches the integrated device of claim 11, wherein the plurality of pillar interconnects comprise:
a first pillar interconnect that vertically overlaps with the encapsulation layer; and
a second pillar interconnect that vertically overlaps with the die interconnection portion. (Fig. 3)
In regards to dependent claim 13, Yasukawa teaches the integrated device of claim 12, wherein the first pillar interconnect does not vertically overlap with the plurality of die interconnects (Fig. 3).
In regards to dependent claim 14, Yasukawa teaches the integrated device of claim 12,
wherein the integrated device comprises:
an inner region; and
a periphery region,
wherein the die interconnection portion is part of the inner region of the integrated device, and
wherein the encapsulation layer is part of the periphery region of the integrated device (Fig. 3, left side vs right side).
In regards to dependent claim 17, Yasukawa teaches the integrated device of claim 14,
wherein the die substrate includes an active region comprising a plurality of logic cells,
wherein the active region is located in the inner region of the integrated device, and
wherein the periphery region is free of any logic cells. (Fig. 7)
In regards to dependent claim 18, Yasukawa teaches the integrated device of claim 17, wherein at least one pillar interconnect does not vertically overlap with the active region (Fig. 7).
In regards to dependent claim 19, Yasukawa teaches the integrated device of claim 11, further comprising a seed layer that is part of the plurality of metallization interconnects ([0103]).
In regards to dependent claim 20, Yasukawa teaches the integrated device of claim 11, further comprising a plurality of solder interconnects coupled to the plurality of pillar interconnects ([0490]).
Allowable Subject Matter
Claim 5,6, 15, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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