Prosecution Insights
Last updated: July 17, 2026
Application No. 18/609,681

PACKAGE SUBSTRATE HAVING STACKED ELECTRONIC COMPONENT STRUCTURE DISPOSED IN A CAVITY OF A CORE

Non-Final OA §102
Filed
Mar 19, 2024
Examiner
OH, JAEHWAN
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 669 resolved
+24.9% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
18 currently pending
Career history
687
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
68.3%
+28.3% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 669 resolved cases

Office Action

§102
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. Patent Application Publication 2024/0038739, hereinafter referred to as Lee). As to claim 1, Lee teaches 1. A substrate, comprising: a core having a cavity; a first set of one or more metallization layers disposed at an upper portion of the core; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure comprises: a first electronic component including an upper surface having a second set of one or more metallization layers and a first set of via structures electrically coupling the first electronic component with the first set of one or more metallization layers, and a second electronic component over the first electronic component, the second electronic component including an upper surface having a third set of one or more metallization layers electrically coupling the second electronic component with the first set of one or more metallization layers. [see 120, 130, 180 in Fig. 1 for example] As to claim 2, Lee teaches 2. The substrate of claim 1, wherein: the second electronic component comprises a deep trench capacitor (DTC). [¶0003~0004] As to claim 3, Lee teaches 3. The substrate of claim 1, wherein: the first electronic component comprises an input/output (I/O) hub. [¶0003~0004] As to claim 4, Lee teaches 4. The substrate of claim 1, wherein: the first electronic component comprises a skew-matching block. [¶0003~0004] As to claim 5, Lee teaches 5. The substrate of claim 1, wherein: the first electronic component comprises a bulk inductor. [¶0003~0004] As to claim 6, Lee teaches 6. The substrate of claim 1, wherein: the first electronic component comprises an input/output (I/O) untangling block. [¶0003~0004] As to claim 7, Lee teaches 7. The substrate of claim 1, wherein the stacked electronic component structure further comprises: a third electronic component disposed alongside the first electronic component, the third electronic component having an upper surface having a third set of one or more metallization layers and a second set of via structures electrically coupling the third electronic component with the first set of one or more metallization layers. [¶0110~0111] As to claim 8, Lee teaches 8. The substrate of claim 7, wherein: the first electronic component and the third electronic component are disposed alongside one another in a common support material. [¶0110~0111] As to claim 9, Lee teaches 9. The substrate of claim 1, wherein: the core has a thickness that is greater than about 780 micrometers. [¶0072] As to claim 10, Lee teaches 10. An electronic device, comprising: a substrate comprising: a core substrate including a core having a cavity; a first set of one or more metallization layers disposed at an upper portion of the cavity; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure comprises: a first electronic component including an upper surface having a second set of one or more metallization layers and a first set of vias electrically coupling the first electronic component with the first set of one or more metallization layers, and a second electronic component over the first electronic component, the second electronic component including an upper surface having a third set of one or more metallization layers electrically coupling the second electronic component with the first set of one or more metallization layers. [see 120, 130, 180 in Fig. 1 for example] As to claim 11, Lee teaches 11. The substrate of claim 10, wherein: the second electronic component comprises a deep trench capacitor (DTC). [¶0003~0004] As to claim 12, Lee teaches 12. The substrate of claim 10, wherein: the first electronic component comprises an input/output (I/O) hub. [¶0003~0004] As to claim 13, Lee teaches 13. The substrate of claim 10, wherein: the first electronic component comprises a skew-matching block. [¶0003~0004] As to claim 14, Lee teaches 14. The substrate of claim 10, wherein: the first electronic component comprises a bulk inductor. [¶0003~0004] As to claim 15, Lee teaches 15. The substrate of claim 10, wherein: the first electronic component comprises an input/output (I/O) untangling block. [¶0003~0004] As to claim 16, Lee teaches 16. The substrate of claim 10, wherein the stacked electronic component structure further comprises: a third electronic component disposed alongside the first electronic component, the third electronic component having an upper surface having a third set of one or more metallization layers and a second set of vias electrically coupling the third electronic component with the first set of one or more metallization layers. [¶0110~0111] As to claim 17, Lee teaches 17. The substrate of claim 16, wherein: the first electronic component and the third electronic component are disposed alongside one another in a common support material. [¶0110~0111] As to claim 18, Lee teaches 18. The substrate of claim 10, wherein: the core has a thickness that is greater than about 780 micrometers. [¶0072] As to claim 19, Lee teaches 19. The electronic device of claim 10, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle. [¶0003~0004] As to claim 20, Lee teaches 20. A method of forming a substrate, comprising: forming a stacked electronic component structure comprising: a first electronic component including an upper surface having a first set of one or more metallization layers and a first set of vias electrically coupling the first electronic component with a first set of one or more pads disposed at an upper surface of the stacked electronic component structure, and a second electronic component over the first electronic component, the second electronic component including an upper surface having a second set of one or more metallization layers electrically coupling the second electronic component with a second set of one or more pads disposed at the upper surface of the stacked electronic component structure; and positioning the stacked electronic component structure in a cavity of a core substrate. [see 120, 130, 180 in Fig. 1 for example] Conclusion Claims 1-20 are rejected as explained above. The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAEHWAN OH/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 19, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 669 resolved cases by this examiner. Grant probability derived from career allowance rate.

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