CTNF 18/609,837 CTNF 100369 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 1 and 18 are objected to because of the following informalities: a typo is present in the phrase “ through a through a plurality of inter substrate interconnects” in line 9, which is being interpreted to read “ through a plurality of inter substrate interconnects” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 2022/0223494 A1 to Lee et al. (hereinafter “Lee”) . Regarding claim 1, Lee discloses a device comprising: a board (101, Fig 41B); a first package coupled to the board through a plurality of solder interconnects (chip 511 having unit 425 coupled to interconnect board 101 through contacts 168 made of solder caps 38, 49; Figs. 5A, 6A-6B, 41A-41B; paragraphs [0126]-[0129], [0381]), wherein the first package comprises: a first substrate; a first integrated device coupled to the first substrate (unit 425 having substrate 2 of memory module 159 with chip 251 stack coupled thereto; Figs. 5A, 6A-6B; paragraphs [0126]-[0129]); a heat pipe coupled to the first integrated device through a thermal interface material (heat pipe pairing 700 coupled to chip 251 stack through fluid chamber 7112 and underfill layer 694; Figs. 8, 41A-41B; paragraphs [0172], [0381]); a second package coupled to the first substrate through a through a plurality of inter substrate interconnects (unit 428 coupled to substrate 2 through interconnects of board 101; Figs. 5A and 41B); and an encapsulation layer located between the first substrate and the second package (underfill layers 694 located between substrate 2 and unit 428; Figs. 5A and 41B). Regarding claim 2, Lee discloses the device of claim 1, wherein the heat pipe is coupled to a back side of the first integrated device through the thermal interface material (heat pipe pairing 700 coupled to back side of chip 251 stack through fluid chamber 7112 and underfill layer 694; Figs. 8, 41A-41B; paragraphs [0172], [0381]). Regarding claim 3, Lee discloses the device of claim 1, wherein the second package comprises a second substrate and a second integrated device coupled to the second substrate; and wherein the device further comprises a heat sink coupled to the second package through a second thermal interface material (unit 428 having module 190 coupled to substrate 2, where unit 428 is coupled to fluid chamber 7112 of heat pipe pairing 700 via thermally conductive adhesive layer 601; Figs. 7A and 41B; paragraph [0381]). Regarding claim 4, Lee discloses the device of claim 3, wherein the heat sink is further coupled to the heat pipe (fluid chamber 7112 coupled to heat pipe pairing 700; Figs. 8 and 41B). Regarding claim 5, Lee discloses the device of claim 1, wherein the second package comprises a second substrate and a second integrated device coupled to the second substrate; and a vapor chamber coupled to the second package through a second thermal interface material (unit 428 having module 190 coupled to substrate 2, where unit 428 is coupled to fluid chamber 7112 of heat pipe pairing 700 via thermally conductive adhesive layer 601; Figs. 7A and 41B; paragraph [0381]). Regarding claim 6, Lee discloses the device of claim 5, wherein the heat sink is further coupled to the heat pipe (fluid chamber 7112 coupled to heat pipe pairing 700; Figs. 8 and 41B). Regarding claim 7, Lee discloses the device of claim 1, wherein the plurality of inter substrate interconnects comprise a plurality of solder interconnects (interconnects of board 101 comprises solder cap balls 33; Figs. 37B and 41B). Regarding claim 8, Lee discloses the device of claim 1, wherein the plurality of inter substrate interconnects comprise a plurality of through encapsulation layer interconnects (interconnects of board 101 are disposed through polymer layers 42 encapsulating other structures; Figs. 37B and 41B). Regarding claim 9, Lee discloses the device of claim 1, wherein the encapsulation layer at least partially encapsulates the plurality of inter substrate interconnects (underfill layers 694 at least partially encapsulate interconnects of board 101; Fig. 41B). Regarding claim 10, Lee discloses the device of claim 1, wherein the heat pipe is a two phase heat dissipation device (heat pipe pairing 700 utilizes liquid and vapor heat dissipation; Fig. 8; paragraph [0172]). Regarding claim 11, Lee discloses the device of claim 1, wherein the heat pipe is embedded in the encapsulation layer (heat pipe pairing 700 is embedded within underfill layers 694; Fig. 41B). Regarding claim 12, Lee discloses the device of claim 1, wherein the encapsulation layer at least partially encapsulates the first integrated device, the plurality of inter substrate interconnects and the heat pipe (underfill layers 694 at least partially encapsulate interconnects of board 101, chip stack 251, and heat pipe pairing 700; Fig. 41B). Regarding claim 13, Lee discloses the device of claim 1, wherein the heat pipe is located laterally between two inter substrate interconnects from the plurality of inter substrate interconnects (top heat pipe 700 located between interconnects running vertically from within board 101; Fig. 41B). Regarding claim 14, Lee discloses the device of claim 1, wherein the heat pipe extends in a horizontal direction and a vertical direction (heat pipe pairing 700 comprises vertical and horizontal dimension; Fig. 41B). Regarding claim 15, Lee discloses the device of claim 14, wherein the heat pipe that extends in a horizontal direction extends in a first horizontal direction and a second horizontal direction (heat pipe pairing 700 comprises three-dimensional structure having two horizontal dimensions; Fig. 41B). Regarding claim 16, Lee discloses the device of claim 14, further comprising a frame coupled to the board (metal plates 567 and dummy chips 367 collectively act as frame coupled to board 101 through which heat pipe pairing 700 extends; Figs. 41A-41B). Regarding claim 17, Lee discloses the device of claim 16, wherein the heat pipe extends through the frame (metal plates 567 and dummy chips 367 collectively act as frame coupled to board 101 through which heat pipe pairing 700 extends; Figs. 41A-41B). Regarding claim 18, Lee discloses a package on package comprising: a first package comprising: a first substrate (substrate 2; Figs. 5A, 6A-6B, 41A-41B); a first integrated device coupled to the first substrate (stacked chip 511 having unit 425 having substrate 2 of memory module 159 with chip 251 stack coupled thereto; Figs. 5A, 6A-6B, 41A-41B; paragraphs [0126]-[0129], [0381]); and a heat pipe coupled to the first integrated device through a thermal interface material (heat pipe pairing 700 coupled to chip 251 stack through fluid chamber 7112 and underfill layer 694; Figs. 8, 41A-41B; paragraphs [0172], [0381]); a second package coupled to the first package through a through a plurality of inter substrate interconnects (unit 428 coupled to substrate 2 through interconnects of board 101; Figs. 5A and 41B); and an encapsulation layer located between the first substrate and the second package (underfill layers 694 located between substrate 2 and unit 428; Figs. 5A and 41B). Regarding claim 19, Lee discloses the package on package of claim 18, wherein the heat pipe is coupled to a back side of the first integrated device through the thermal interface material (heat pipe pairing 700 coupled to back side of chip 251 stack through fluid chamber 7112 and underfill layer 694; Figs. 8, 41A-41B; paragraphs [0172], [0381]). Regarding claim 20, Lee discloses the package on package of claim 18, wherein the second package comprises: a second substrate; and a second integrated device coupled to the second substrate, and wherein the package on package further comprises a heat sink coupled to the second package through a second thermal interface material (unit 428 having module 190 coupled to substrate 2, where unit 428 is coupled to fluid chamber 7112 of heat pipe pairing 700 via thermally conductive adhesive layer 601; Figs. 7A and 41B; paragraph [0381]). Conclusion The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2021/0225708 A1 to Lee et al., US 2011/0260303 A1 to Pagaila et al., and US 2023/0187408 A1 to Yu et al. each discloses bonded packages with heat pipes and other structures arranged similar to the presently claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/609,837 Page 2 Art Unit: 2818 Application/Control Number: 18/609,837 Page 3 Art Unit: 2818 Application/Control Number: 18/609,837 Page 4 Art Unit: 2818 Application/Control Number: 18/609,837 Page 5 Art Unit: 2818 Application/Control Number: 18/609,837 Page 6 Art Unit: 2818 Application/Control Number: 18/609,837 Page 7 Art Unit: 2818 Application/Control Number: 18/609,837 Page 8 Art Unit: 2818
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