DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claim 1 “wherein the insulating layer increases in thickness toward a bottom portion of the memory device” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 2016/0149004 A1) (“Rabkin”), in view of Saito et al. (US 2011/0133182 A1) (“Saito”), and/or in view of Ryu et al. (KR 2018-0020024 A) (“Ryu”), by means of Examiner provided machine translation in the parent Application.
Regarding claim 1, Rabkin teaches at least in figures 3B, 4A, and 5A-B:
A stack of multilayers (696-698) comprising at least one transition metal (¶ 0046, where 696 and 698 can comprise Al2O3; see claim 5 where Al can be one of the transition metals); and
A plurality of channel layer (699) arranged horizontally (see at least figure 3A where there can be a plurality of devices) and formed adjacent to the multilayers (696-698) and configured to comprise an indium gallium oxide (IGO) material (¶ 0026);
an insulating layer (D0-D8) and an electrode layer (WL0-WL6), which are alternately stacked vertically (shown in figure 3B),
wherein the multilayers (696-698) consist of a tunneling oxide layer (698), a charge trap layer (697), and a blocking oxide layer (696), which are sequentially stacked (they are so stacked) and the stack of multilayers are orthogonally arranged with respect to the insulating layer and the electrode layer (this is shown in the combination of figure 3B and figure 8),
wherein each of the plurality of the channel layers has a hollow tube-shaped interior and a filling layer placed inside the hollow tube-shaped interior (the device of figure 8 can be considered a hollow tube-shaped interior filled with a filling layer 695), and
wherein the each of the plurality of channel layers (699) comprises (detailed below)
a drain region (top of 699 near 811) and a conductive pattern (811) formed on the drain region (top of 699 near 811),
said conductive pattern (811) being connected to a common bit line extending horizontally through the horizontally aligned channel layers (111; where 111 so extends based upon figure 4A),
wherein the IGO material is deposited to a thickness of 10nm to 20nm (¶ 0100, where the thickness can be from 10nm to 25nm).
wherein each of the electrode layers (WL0-WL6) operates as a control gate ( as shown in figure 1 each of the WL lines are connected to a gate).
Regarding the limitation,
Wherein the IGO material has a (222) crystal plane and IGO material exhibits a field-effect mobility of 30 cm2/Vs or more.
Based upon Applicant’s disclosure at page 15-16, the above characteristics happen when the IGO material is annealed at 650-750 C. Rabkin teaches an anneal temperature of 600C C. ¶ 0099.
Rabkin does not teach the same temperature range as disclosed by Applicant.
Saito teaches:
An oxide semiconductor device with a channel comprising indium, gallium, and oxygen. ¶ 0133-35. Saito also teaches that the post formation anneal can be performed by a plurality of different means, ¶ 0148, and this anneal can be performed at 650-750C, ¶ 0149.
It would have been obvious to one of ordinary skill in the to use this higher anneal temperature taught by Rabkin as Saito’s heat treatment (anneal) has the effect of dehydrating or dehydrogenating the oxide semiconductor layer. ¶ 0153.
Based upon the process described by Rabkin and Saito it would have been obvious that one of ordinary skill in the art would have gotten the claimed characteristics “wherein the IGO material has a (222) crystal plane and IGO material exhibits a field-effect mobility of 30 cm2/Vs or more” as the prior art uses the same process to form the IGO material.
Alternatively, or additionally, it would have been obvious to one of ordinary skill in the art to combine Rabkin and Saito because when IGO is anneal above 300 °C it changes from an amorphous phase to a crystalline phase. ¶| 0025. Further, Ryu teaches that when one anneals higher than 300 °C one can get an increase in drain current. Figures 3a-d. Which further leads to a greater on/off current. ¶ 0029.
Therefore, it would have been obvious to one of ordinary skill in the art to anneal the IGO layer to a temperature above 300 °C.
Further, based upon the teachings of Ryu it would have been obvious to one of ordinary skill in the art to raise the anneal, or thermal treatment, temperature above 600 °C because based upon the teachings of Ryu it would lead to a greater current through the device and lead to a greater on/off ratio. It would have been obvious to one of ordinary skill in the art to do this for a memory device in order to reduce the leakage current through the memory device, and to get more separation between voltage levels when writing data to the memory device.
In addition to the above, Ryu teaches that when one anneals IGO to a temperature above 300 °C one crystallizes the IGO material and obviously gets the IGO material to have a (222) plane. ¶ 0022. Therefore, this limitation “wherein the IGO material has a (222) crystal plane and IGO material exhibits a field-effect mobility of 30 cm2/Vs or more” is obvious characteristic of IGO when IGO is anneal at the temperature ranges which are taught and obvious in view of Ryu.
Thus, the combination of Ryu with Rabkin and Saito teach the claimed limitaions.
Regarding the limitation,
wherein the insulating layer increases in thickness toward a bottom portion of the memory device.
Applicant states they have support for this limitation in ¶ 0054 of the PgPug. Pg. 9 at ¶ 5. This paragraph states in full:
Here, the plural interlayer insulating layers 140 may be a silicon oxide film or a silicon nitride film and may have the same ore different thicknesses. For example, the plural interlayer insulating layers 140 may be formed to have a thicker thickness toward the bottom.
When compared to the prior art there is no criticality or unexpected results arising from having the insulating layer to be thicker near the bottom. Under MPEP 2144.04(IV)(A), the Court has held “where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.” Here the only difference between the prior art and the claimed device is the relative dimension of the bottom part of the interlayer insulating layer. Therefore, as no criticality or unexpected results have been disclosed the claimed relative dimension does not render the claim patentably distinct from the prior art.
Regarding claim 2, Rabkin teaches at least in figures 5A-B:
wherein the plurality of channel layer comprise the IGO (See claim 1) material crystallized through thermal treatment performed in a temperature range of 650 to 750 (The claim is directed to a device. This limitation is directed to a process. It appears that this claim is attempting to claim that the IGO material is crystallized. The abstract of Rabkin teaches the IGO material may be crystalline in structure. In addition, figure 6 of Rabkin teaches a crystalline structure.).
Regarding claim 4, Rabkin teaches at least in figures 5A-B:
wherein the multilayers (696-698) are oxide-nitride-oxide (ONO) layers (¶ 0046).
Regarding claim 5, Rabkin teaches at least in figures 5A-B:
wherein the transition metal comprises aluminum (Al), titanium (Ti) and titanium nitride (TiN) (see claim 1 where Al can used), or a combination thereof.
Regarding claim 6,
Claim 6 is a characteristic of the IGO material. Because the IGO material is formed in the same manner as Applicant it is obvious that it would have the same memory window voltage characteristic as claimed.
Regarding claim 7,
wherein the tunneling oxide layer (Rabkin 698) is formed of an aluminum oxide material (¶ 0046, where 698 can comprise oxides and/or nitrides. The oxides and nitrides are described in ¶ 0046 as being SiN, AlO, and SiO2. Therefore it would have been obvious based upon the teachings of Rabkin the tunneling oxide layer could have been formed of AlO, aluminum oxide),
the charge trap layer (Rabkin 697) is formed of a silicon nitride material (¶ 0046, where 697 can be SiN), and
the blocking oxide layer (Rabkin 696) is formed of silicon oxide material (¶ 0046, where 696 can comprise SiO2).
Response to Arguments
Applicant’s amendments, filed December 11, 2025, with respect to the rejection(s) of the claims have been fully considered, and do not overcome the art of record. Examiner has changed the grounds of rejection from a 102 to a 103.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898