DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Aug. 4th, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims and Specification (Title) have overcome each and every objection previously set forth in the Non-Final Office Action mailed on May 20th, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220052046) in view of Kim et al. (US 20220209013).
Regarding claim 1, Choi teaches a semiconductor device (Abstract), comprising:
a substrate (fig. 2A, substrate 102; para. 0029) comprising an active pattern (fin-type active areas FA; para. 0029);
a channel pattern (nanosheet stacks NSS; para. 0029) on the active pattern (FA), the channel pattern (NSS) comprising a first semiconductor pattern (nanosheet N1; para. 0032), a second semiconductor pattern (nanosheet N2; para. 0032), and a third semiconductor pattern (nanosheet N3; para. 0032) sequentially stacked and vertically spaced apart, such that the first semiconductor pattern (N1) is the lowermost semiconductor pattern (N1 is the bottom one) among the first semiconductor pattern (N1), the second semiconductor pattern (N2), and the third semiconductor pattern (N3);
a source/drain pattern (source/drain areas 130; para. 0037) on the active pattern (FA); and
a gate electrode (main-gate portion 160M or gate line 160; para. 0049) on the first semiconductor pattern (N1), the second semiconductor pattern (N2), and the third semiconductor pattern (N3),
wherein the source/drain pattern (130) comprises a buffer layer (outer blocking layer 132; para. 0039) and a main layer (inner blocking layer 134, main body layer 136; para. 0039) on the buffer layer (132),
wherein the main layer (134, 136) comprises silicon (136 may include a Si1-xGex layer; para. 0039) that is doped with an impurity (dopant of phosphorus (P), arsenic (As), and antimony (Sb); para. 0039),
wherein an impurity concentration (dopant) of the main layer (134, 136) is a first atomic fraction (dopant at bottom level) at a first level (top level) corresponding to the first semiconductor pattern (N1),
wherein the impurity concentration (dopant) of the main layer (134, 136) is a second atomic fraction (dopant at middle level) at a second level (middle level) corresponding to the second semiconductor pattern (N2),
wherein the impurity concentration (dopant) of the main layer (134, 136) is a third atomic fraction (dopant at top level) at a third level (bottom level) corresponding to the third semiconductor pattern (N3).
Choi fails to explicitly teach the first atomic fraction is greater than the third atomic fraction.
However, Kim teaches the first atomic fraction (Kim: Annotated fig. 3, square of second epitaxial layer 150B at channel layer 141 level; para. 0024, 0053, similar to N1 of Choi) is greater (Kim: 150B has 1.5 to 15 times the impurity concentration of 150A; para. 0053) than the third atomic fraction (Kim: circle of first epitaxial layer 150A at channel layer 143 level; para. 0024, 0053, similar to N3 of Choi).
Kim and Choi are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first atomic fraction is greater than the third atomic fraction as taught by Kim.
Doing so would realize epitaxial layers structure to improve electrical characteristics (Kim: para. 0051).
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(Annotated fig. 3)
Regarding claim 2, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein the second atomic fraction (Kim: Annotated fig. 3, triangle of half 150A/150B at channel layer 142 level; para. 0024, similar to N2 of Choi) is greater than the third atomic fraction (Kim: 150A at 143), and
wherein the second atomic fraction (Kim: half 150A/150B at 142) is less than the first atomic fraction (Kim: 150B at 141).
Regarding claim 3, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein the impurity concentration of the main layer (Kim: Annotated fig. 3, concentration of 150, similar to 134, 136 of Choi) decreases from the first level (Kim: 150B at 141) to the third level (Kim: 150A at 143 along a diagonal direction).
Regarding claim 4, Choi in view of Kim further teaches the semiconductor device of claim 1 including the first atomic fraction (Kim: Annotated fig. 3, 150B at 141).
Choi in view of Kim as applied to claim 1 above fails to explicitly teach the first atomic fraction is in a range from 4 at% to 12 at%, and
wherein the third atomic fraction is in a range from 2 at% to 10 at%.
However, Kim teaches the first atomic fraction (Kim: Annotated fig. 3, 150B at 141) is around 0.5%~12% (1.5 to 15 times of 0.3 at % or more and 8.0 at % or less; para. 0052-0053), which overlaps in a range from 4 at% to 12 at%, and
wherein the third atomic fraction (Kim: 150A at 143) is around 0.3%~8% (0.3 at % or more and 8.0 at % or less; para. 0052), which overlaps in a range from 2 at% to 10 at%.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first atomic fraction range from 0.5%~12% to from 4 at% to 12 at%, and the third atomic fraction from 0.3%~8% to from 2 at% to 10 at%.
Doing so would realize epitaxial layers structure to improve electrical characteristics (Kim: para. 0051). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 5, Choi in view of Kim further teaches the semiconductor device of claim 1 including the first atomic fraction (Kim: Annotated fig. 3, 150B at 141).
Choi in view of Kim as applied to claim 1 above fails to explicitly teach a difference between the first atomic fraction and the third atomic fraction is in a range from 0.5 at% to 2 at%.
However, Kim teaches a difference between the first atomic fraction and the third atomic fraction (Kim: Annotated fig. 3, difference of 150B and 150A) is around 0.2%~4% (Kim: 0.5 times of 0.3 at % or more and 8.0 at % or less; para. 0052-0053), which overlaps in a range from 0.5 at% to 2 at%.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the first atomic fraction and the third atomic fraction range from 0.2%~4% to from 0.5 at% to 2 at%.
Doing so would realize epitaxial layers structure to improve electrical characteristics (Kim: para. 0051). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 6, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein the impurity (Choi: dopant) is at least one of phosphorus, arsenic, an antimony (Choi: phosphorus (P), arsenic (As), and antimony (Sb); para. 0039).
Regarding claim 7, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein the main layer (Kim: fig. 3, 150) further comprises a first epitaxial layer (Kim: 150B) and a second epitaxial layer (Kim: 150A attach) on the first epitaxial layer (Kim: 150B), and
wherein an impurity concentration of the first epitaxial layer (Kim: impurity concentration of 150B) is higher than an impurity concentration of the second epitaxial layer (Kim: impurity concentration of 150A).
Regarding claim 8, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein the gate electrode (Choi: fig. 2A, gate lines 160 including 160M; para. 0049) comprises an inner electrode (Choi: sub-gate portions 160S; para. 0049) between the first semiconductor pattern (Choi: N3) and the second semiconductor pattern (Choi: N2), and
wherein the buffer layer (Choi: 132) is between the main layer (Choi: 134, 136) and the inner electrode (Choi: 160S).
Regarding claim 9, Choi in view of Kim further teaches the semiconductor device of claim 8, further comprising a gate insulating layer (Choi: fig. 2A, gate dielectric layer 152; para. 0052) between the inner electrode (Choi: 160S) and the buffer layer (Choi: 132),
wherein the gate insulating layer (Choi: 152) directly contacts the buffer layer (Choi: 132).
Regarding claim 10, Choi in view of Kim further teaches the semiconductor device of claim 1, wherein a length of the first semiconductor pattern (Choi: fig. 2A, top width of N3) is greater than a length of the third semiconductor pattern (Choi: top width of N1).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Lin et al. (US 20220367726).
Regarding claim 11, Choi teaches a semiconductor device (Abstract), comprising:
a substrate (fig. 2A, substrate 102; para. 0029) comprising an active pattern (fin-type active areas FA; para. 0029);
a channel pattern (nanosheet stacks NSS; para. 0029) on the active pattern (FA), the channel pattern (NSS) comprising a plurality of semiconductor patterns (nanosheets N1, N2, N3; para. 0032) stacked and vertically spaced apart;
a source/drain pattern (source/drain areas 130; para. 0037) on the active pattern (FA); and
a gate electrode (main-gate portion 160M or gate line 160; para. 0049) on the plurality of semiconductor patterns (N1, N2, N3),
wherein the source/drain pattern (130) comprises an impurity (dopant of phosphorus (P), arsenic (As), and antimony (Sb); para. 0039),
wherein the impurity (dopant) comprises at least one of phosphorus, arsenic, and antimony (phosphorus (P), arsenic (As), and antimony (Sb); para. 0039),
wherein an uppermost semiconductor pattern (N3) of the plurality of semiconductor patterns is located at a first level (top level),
wherein a lowermost semiconductor pattern (N1) of the plurality of semiconductor patterns is located at a second level (bottom level).
Choi fails to explicitly teach an impurity concentration of the source/drain pattern increases from the first level to the second level.
However, Lin teaches an impurity concentration (Lin: fig. 21, annotated fig. 22, dopant of layers L1, L2; para. 0048) of the source/drain pattern (Lin: source/drain layer 2102, 2104; para. 0060, similar to 130 of Choi) increases (Lin: L2 has higher dopant concentration than L1; para. 0048) from the first level (Lin: top level circle in L1) to the second level (Lin: bottom level square in L2).
Lin and Choi are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an impurity concentration of the source/drain pattern increases from the first level to the second level as taught by Lin.
Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017).
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(annotated fig. 22)
Regarding claim 12, Choi in view of Lin further teaches the semiconductor device of claim 11 including the first level (Lin: annotated fig. 22, top level circle in L1)
Choi in view of Lin as applied to claim 11 above fails to explicitly teach the impurity concentration of the source/drain pattern at the first level is in a range from 4 at% to 12 at%, and
wherein the impurity concentration of the source/drain pattern at the second level is in a range from 2 at% to 10 at%.
However, Lin teaches the impurity concentration of the source/drain pattern at the first level (Lin: annotated fig. 22, top level circle in L1) is around 1%~10% (Lin: L1 of 5-10×10^20 atoms/cm3 with edge of L2 of 1-5×10^21 atoms/cm3, which can be calculated as 1%~10% doping; para. 0048), which overlaps a range from 4 at% to 12 at%, and
wherein the impurity concentration of the source/drain pattern at the second level (Lin: bottom level square in L2) is around 2%~10% (Lin: L2 of 1-5×10^21 atoms/cm3, which can be calculated as 2%~10% doping; para. 0048), which overlaps in a range from 2 at% to 10 at%.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the impurity concentration of the source/drain pattern at the first level range from around 1%~10% to from 4 at% to 12 at%, and the impurity concentration of the source/drain pattern at the second level from around 2%~10% to from 2 at% to 10 at%.
Doing so would realize higher doping concentration to improve contact resistance (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 13, Choi in view of Lin further teaches the semiconductor device of claim 11 including the first level (Lin: annotated fig. 22, top level circle in L1).
Choi in view of Lin as applied to claim 11 above fails to explicitly teach a difference between the impurity concentration of the source/drain pattern measured at the first level and the impurity concentration of the source/drain pattern measured at the second level is in a range from 0.5 at% to 2 at%.
However, Lin teaches a difference between the impurity concentration of the source/drain pattern measured at the first level (Lin: annotated fig. 22, top level circle in L1) and the impurity concentration of the source/drain pattern measured at the second level (Lin: bottom level square in L2) is around 1%~8% (Lin: Based on L2 of 1-5×10^21 atoms/cm3 and L1 of 5-10×10^20 atoms/cm3, which can be calculated as difference between 2%~10% and 1%~2% doping; para. 0048), which overlaps in a range from 0.5 at% to 2 at%.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the impurity concentration of the source/drain pattern measured at the first level and the impurity concentration of the source/drain pattern measured at the second level from 1%~8% to from 0.5 at% to 2 at%.
Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 14, Choi in view of Lin further teaches the semiconductor device of claim 11, wherein a length of the uppermost semiconductor pattern (Choi: fig. 2A, top width of N3) of the plurality of semiconductor patterns is greater than a length of the lowermost semiconductor pattern (Choi: top width of N1) of the plurality of semiconductor patterns.
Regarding claim 15, Choi in view of Lin further teaches the semiconductor device of claim 11, wherein the source/drain pattern (Choi: fig. 2A, 130) further comprises a buffer layer (Choi: outer blocking layer 132; para. 0039) and a main layer (Choi: inner blocking layer 134, main body layer 136; para. 0039) on the buffer layer (132), and
wherein the main layer (Choi: 134, 136) extends from the first level (top level) to the second level (bottom level).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220045103) (“KIM2”) in view of Kim.
Regarding claim 16, KIM2 teaches a semiconductor device (Abstract), comprising:
a substrate (fig. 2B, support substrate 100; para. 0029) comprising an n-type metal-oxide-semiconductor (MOS) field effect transistor (FET) (NMOSFET) region (NMOSFET region NR; para. 0031);
an active pattern (second semiconductor pattern 102b; para. 0032) on the NMOSFET region (NR);
a channel pattern (second channel structures CH2; para. 0032) on the active pattern (102b), the channel pattern (CH2) comprising a plurality of semiconductor patterns (first channel pattern SP1, second channel pattern SP2, third channel pattern SP3; para. 0032) stacked and spaced apart, the plurality of semiconductor patterns comprising a first semiconductor pattern (SP1), a second semiconductor pattern (SP2) adjacent to the first semiconductor pattern (SP1), and an uppermost semiconductor pattern (SP3), the first semiconductor pattern (SP1) being a lowermost semiconductor pattern (SP1 is the bottom one) among the plurality of semiconductor patterns (SP1-3);
a source/drain pattern (first and second source/drain patterns SD1, SD2; para. 0034) on the active pattern (102b) and comprising an impurity (dopant; para. 0034);
a gate electrode (gate electrode GE; para. 0044) on the channel pattern (CH2), the gate electrode (GE) comprising an inner electrode (second portion PO2; para. 0038) between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2), and an outer electrode (fourth portion PO4; para. 0038) on the uppermost semiconductor pattern (SP3);
a gate insulating layer (gate insulating layer GI; para. 0040) between the inner electrode (PO2) and the source/drain pattern (SD2);
a gate spacer (gate spacers GS; para. 0043) on a side surface of the outer electrode (PO4);
a gate capping pattern (gate capping pattern GP; para. 0044) on a top surface of the outer electrode (GE);
an interlayer insulating layer (second interlayer insulating layers 120; para. 0044) on the gate capping pattern (GP) and the source/drain pattern (SD2);
a gate contact (fig. 2D, gate contact GC; para. 0050) connected to the gate electrode (GE) and penetrating the interlayer insulating layer (120) and the gate capping pattern (GP);
an active contact (fig. 2C, source/drain contacts AC; para. 0050) connected to the source/drain pattern (SD2) and penetrating the interlayer insulating layer (120); and
a first metal layer (first metal layer M1; para. 0052) on the interlayer insulating layer (120),
wherein the first metal layer (M1) comprises first interconnection lines (lower vias VI1; para. 0053) respectively connected to the gate contact (GC) and the active contact (AC),
wherein a length of the first semiconductor pattern (fig. 2D, width of SP1) is greater than a length of the second semiconductor pattern (width of SP2).
KIM2 fails to explicitly teach an impurity concentration of the source/drain pattern is a first atomic fraction at a first level corresponding to the first semiconductor pattern,
wherein the impurity concentration of the source/drain pattern is a second atomic fraction at a second level corresponding to the second semiconductor pattern, and
wherein the first atomic fraction is greater than the second atomic fraction.
However, Kim teaches an impurity concentration of the source/drain pattern (Kim: Annotated fig. 3, impurity concentration of source/drain regions 150; para. 0025, similar to SD1 of KIM2) is a first atomic fraction (Kim: square of second epitaxial layer 150B at channel layer 141 level; para. 0024, 0053) at a first level (bottom level) corresponding to the first semiconductor pattern (Kim: 141, similar to SP1 of KIM2),
wherein the impurity concentration of the source/drain pattern (Kim: impurity concentration of 150) is a second atomic fraction (Kim: triangle of half first epitaxial layer 150A/150B at channel layer 142 level; para. 0024, 0053) at a second level (middle level) corresponding to the second semiconductor pattern (Kim: 142, similar to SP2 of KIM2), and
wherein the first atomic fraction (Kim: 150B at 141) is greater (Kim: 150B has 1.5 to 15 times the impurity concentration of 150A; para. 0053) than the second atomic fraction (Kim: half 150A/150B at 142).
Kim and KIM2 are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first atomic fraction is greater than the second atomic fraction as taught by Kim.
Doing so would realize epitaxial layers structure to improve electrical characteristics (Kim: para. 0051).
Regarding claim 17, KIM2 in view of Kim further teaches the semiconductor device of claim 16, wherein the gate insulating layer (KIM2: fig. 3A, GI) directly contacts the source/drain pattern (KIM2: SD1).
Regarding claim 18, KIM2 in view of Kim further teaches the semiconductor device of claim 16, wherein the impurity (Kim: doped with) is at least one of phosphorus, arsenic, and antimony (Kim: As, P; para. 0075).
Regarding claim 19, KIM2 in view of Kim further teaches the semiconductor device of claim 16 including the first atomic fraction (Kim: Annotated fig. 3, 150B at 141).
KIM2 in view of Kim as applied to claim 16 above fails to explicitly teach a difference between the first atomic fraction and the second atomic fraction is in a range from 0.5 at% to 2 at%.
However, Kim teaches a difference between the first atomic fraction and the second atomic fraction (Kim: Annotated fig. 3, difference of 150B and half 150A/150B) is around 0.1%~2% (Kim: 0.25 times of 0.3 at % or more and 8.0 at % or less; para. 0052-0053), which overlaps in a range from 0.5 at% to 2 at%.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the first atomic fraction and the third atomic fraction range from 0.1%~2% to from 0.5 at% to 2 at%.
Doing so would realize epitaxial layers structure to improve electrical characteristics (Kim: para. 0051). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 20, KIM2 in view of Kim further teaches the semiconductor device of claim 16, wherein the first level (KIM2: fig. 2B, SP1) is lower than the second level (KIM2: SP2).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 and 16-20 of prior art rejections (35 USC 102/103) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed on Aug. 4th, 2026 have been fully considered but they are not persuasive.
With respect to pages 13 of applicant’s response of claim 1 is rejected under 35 U.S.C.103.
Applicant submits "at least the feature of "wherein an impurity concentration of the source/drain pattern increases from the first level to the second level" is the opposite configuration of Lin, and one of skill in the art would not modify any other reference to have the above quote feature, as Lin provides no motivation for doing so because the configuration of Lin effectively teaches an opposite configuration".
The examiner respectfully disagrees.
As shown in annotated fig. 22 of Lin, although the trace of dose decreases from top to bottom, the dopant concentration is still dominated (more than an order difference) by the changing from inside L2 to outside L1. The claim language just requests an impurity concentration at each level, given a broadest reasonable interpretation, the impurity concentration increases from the first level (top level circle in L1) to the second level (bottom level square in L2), because the impurity concentration increases from outside L1 to inside L2. In addition, as cited in para. 0017 of Lin, Lin teaches motivation of two layers structure with dopant gradient within the source/drain epitaxial features to improve source/drain features.
As result, given a broadest reasonable interpretation, Choi in view of Lin teaches all limitations of claims 11. Details of rejections are discussed above
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
