CTNF 18/609,885 CTNF 97669 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections 07-29-01 AIA Claim 6 is objected to because of the following informalities: In claim 6, line 2, “an antimony" should read “and antimony” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220052046) in view of Lin et al. (US 20220367726) . Regarding claim 1 , Choi teaches a semiconductor device (Abstract), comprising: a substrate (fig. 2A, substrate 102; para. 0029) comprising an active pattern (fin-type active areas FA; para. 0029); a channel pattern (nanosheet stacks NSS; para. 0029) on the active pattern (FA), the channel pattern (NSS) comprising a first semiconductor pattern (nanosheet N3; para. 0032), a second semiconductor pattern (nanosheet N2; para. 0032), and a third semiconductor pattern (nanosheet N1; para. 0032) sequentially stacked and vertically spaced apart; a source/drain pattern (source/drain areas 130; para. 0037) on the active pattern (FA); and a gate electrode (main-gate portion 160M or gate line 160; para. 0049) on the first semiconductor pattern (N3), the second semiconductor pattern (N2), and the third semiconductor pattern (N1), wherein the source/drain pattern (130) comprises a buffer layer (outer blocking layer 132; para. 0039) and a main layer (inner blocking layer 134, main body layer 136; para. 0039) on the buffer layer (132), wherein the main layer (134, 136) comprises silicon (136 may include a Si1-xGex layer; para. 0039) that is doped with an impurity (dopant of phosphorus (P), arsenic (As), and antimony (Sb); para. 0039), wherein an impurity concentration (dopant) of the main layer (134, 136) is a first atomic fraction (dopant at top level) at a first level (top level) corresponding to the first semiconductor pattern (N3), wherein the impurity concentration (dopant) of the main layer (134, 136) is a second atomic fraction (dopant at middle level) at a second level (middle level) corresponding to the second semiconductor pattern (N2), wherein the impurity concentration (dopant) of the main layer (134, 136) is a third atomic fraction (dopant at bottom level) at a third level (bottom level) corresponding to the third semiconductor pattern (N1). Choi fails to explicitly teach the first atomic fraction is greater than the third atomic fraction. However, Lin teaches the first atomic fraction (Lin: fig. 21, 22, region SD1 with 80~100%; para. 0047, similar to dopant at top level) is greater than the third atomic fraction (Lin: region SD3 with 20~60%; para. 0047, similar to dopant at bottom level). Lin and Choi are considered to be analogous to the claimed invention because they are in the same field of transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first atomic fraction is greater than the third atomic fraction as taught by Lin. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Regarding claim 2 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein the second atomic fraction (Lin: fig. 21, 22, region SD2 with 60~80%; para. 0047, similar to dopant at middle level) is greater than the third atomic fraction (Lin: SD3), and wherein the second atomic fraction (Lin: SD2) is less than the first atomic fraction (Lin: SD1). Regarding claim 3 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein the impurity concentration of the main layer (Lin: fig. 21, 22, ion implantation dose distribution 2206; para. 0047, similar to dopant in 134, 136 of Choi) decreases from the first level (Lin: SD1) to the third level (Lin: SD3). Regarding claim 4 , Choi in view of Lin further teaches the semiconductor device of claim 1 including the first atomic fraction (Lin: fig. 22, SD1). Choi in view of Lin as applied to claim 1 above fails to explicitly teach the first atomic fraction is in a range from 4 at% to 12 at%, and wherein the third atomic fraction is in a range from 2 at% to 10 at%. However, Lin teaches the first atomic fraction (Lin: fig. 22, SD1) is around 2%~10% (Lin: SD1 is 80~100% of 1-5×1021 atoms/cm3, which can be calculated as 2%~10% doping; para. 0048), which overlaps in a range from 4 at% to 12 at%, and wherein the third atomic fraction (Lin: SD3) is around 1%~8% (Lin: SD2 is 60~80% of 1-5×1021 atoms/cm3, which can be calculated as 1%~8% doping; para. 0048), which overlaps in a range from 2 at% to 10 at%. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first atomic fraction range from 2%~10% to from 4 at% to 12 at%, and the third atomic fraction from 1%~8% to from 2 at% to 10 at%. Doing so would realize higher doping concentration to improve contact resistance (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 5 , Choi in view of Lin further teaches the semiconductor device of claim 1 including the first atomic fraction (Lin: fig. 22, SD1). Choi in view of Lin as applied to claim 1 above fails to explicitly teach a difference between the first atomic fraction and the third atomic fraction is in a range from 0.5 at% to 2 at%. However, Lin teaches a difference between the first atomic fraction and the third atomic fraction (Lin: fig. 22, difference between SD1 80~100% and SD3 60~80%) is around 1%~2% (Based on 1-5×1021 atoms/cm3 doping, which can be calculated as difference between 2%~10% and 1%~8% doping; para. 0048), which overlaps in a range from 0.5 at% to 2 at%. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the first atomic fraction and the third atomic fraction range from 1%~2% to from 0.5 at% to 2 at%. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 6 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein the impurity (Choi: dopant) is at least one of phosphorus, arsenic, an antimony (Choi: phosphorus (P), arsenic (As), and antimony (Sb); para. 0039). Regarding claim 7 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein the main layer (Lin: fig. 21, layers L1, L2; para. 0045, similar to 134, 136 of Choi) further comprises a first epitaxial layer (Lin: L2) and a second epitaxial layer (Lin: L1) on the first epitaxial layer (Lin: L2), and wherein an impurity concentration of the first epitaxial layer (Lin: L2) is higher (Lin: L2 has higher dopant concentration than L1; para. 0048) than an impurity concentration of the second epitaxial layer (Lin: L1). Regarding claim 8 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein the gate electrode (Choi: fig. 2A, gate lines 160 including 160M; para. 0049) comprises an inner electrode (Choi: sub-gate portions 160S; para. 0049) between the first semiconductor pattern (Choi: N3) and the second semiconductor pattern (Choi: N2), and wherein the buffer layer (Choi: 132) is between the main layer (Choi: 134, 136) and the inner electrode (Choi: 160S). Regarding claim 9 , Choi in view of Lin further teaches the semiconductor device of claim 8, further comprising a gate insulating layer (Choi: fig. 2A, gate dielectric layer 152; para. 0052) between the inner electrode (Choi: 160S) and the buffer layer (Choi: 132), wherein the gate insulating layer (Choi: 152) directly contacts the buffer layer (Choi: 132). Regarding claim 10 , Choi in view of Lin further teaches the semiconductor device of claim 1, wherein a length of the first semiconductor pattern (Choi: fig. 2A, top width of N3) is greater than a length of the third semiconductor pattern (Choi: top width of N1). Regarding claim 11 , Choi teaches a semiconductor device (Abstract), comprising: a substrate (fig. 2A, substrate 102; para. 0029) comprising an active pattern (fin-type active areas FA; para. 0029); a channel pattern (nanosheet stacks NSS; para. 0029) on the active pattern (FA), the channel pattern (NSS) comprising a plurality of semiconductor patterns (nanosheets N1, N2, N3; para. 0032) stacked and vertically spaced apart; a source/drain pattern (source/drain areas 130; para. 0037) on the active pattern (FA); and a gate electrode (main-gate portion 160M or gate line 160; para. 0049) on the plurality of semiconductor patterns (N1, N2, N3), wherein the source/drain pattern (130) comprises an impurity (dopant of phosphorus (P), arsenic (As), and antimony (Sb); para. 0039), wherein the impurity (dopant) comprises at least one of phosphorus, arsenic, and antimony (phosphorus (P), arsenic (As), and antimony (Sb); para. 0039), wherein an uppermost semiconductor pattern (N3) of the plurality of semiconductor patterns is located at a first level (top level), wherein a lowermost semiconductor pattern (N1) of the plurality of semiconductor patterns is located at a second level (bottom level). Choi fails to explicitly teach an impurity concentration of the source/drain pattern increases from the first level to the second level. However, Lin teaches an impurity concentration (Lin: fig. 21, annotated fig. 22, dopant of layers L1, L2; para. 0048) of the source/drain pattern (Lin: source/drain layer 2102, 2104; para. 0060, similar to 130 of Choi) increases (Lin: L2 has higher dopant concentration than L1; para. 0048) from the first level (Lin: top level circle in L1) to the second level (Lin: bottom level square in L2). Lin and Choi are considered to be analogous to the claimed invention because they are in the same field of transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an impurity concentration of the source/drain pattern increases from the first level to the second level as taught by Lin. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). PNG media_image1.png 412 575 media_image1.png Greyscale (annotated fig. 22) Regarding claim 12 , Choi in view of Lin further teaches the semiconductor device of claim 11 including the first level (Lin: annotated fig. 22, top level circle in L1) Choi in view of Lin as applied to claim 11 above fails to explicitly teach the impurity concentration of the source/drain pattern at the first level is in a range from 4 at% to 12 at%, and wherein the impurity concentration of the source/drain pattern at the second level is in a range from 2 at% to 10 at%. However, Lin teaches the impurity concentration of the source/drain pattern at the first level (Lin: annotated fig. 22, top level circle in L1) is around 1%~10% (Lin: L1 of 5-10×10^20 atoms/cm3 with edge of L2 of 1-5×10^21 atoms/cm3, which can be calculated as 1%~10% doping; para. 0048), which overlaps a range from 4 at% to 12 at%, and wherein the impurity concentration of the source/drain pattern at the second level (Lin: bottom level square in L2) is around 2%~10% (Lin: L2 of 1-5×10^21 atoms/cm3, which can be calculated as 2%~10% doping; para. 0048), which overlaps in a range from 2 at% to 10 at%. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the impurity concentration of the source/drain pattern at the first level range from around 1%~10% to from 4 at% to 12 at%, and the impurity concentration of the source/drain pattern at the second level from around 2%~10% to from 2 at% to 10 at%. Doing so would realize higher doping concentration to improve contact resistance (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 13 , Choi in view of Lin further teaches the semiconductor device of claim 11 including the first level (Lin: annotated fig. 22, top level circle in L1). Choi in view of Lin as applied to claim 11 above fails to explicitly teach a difference between the impurity concentration of the source/drain pattern measured at the first level and the impurity concentration of the source/drain pattern measured at the second level is in a range from 0.5 at% to 2 at%. However, Lin teaches a difference between the impurity concentration of the source/drain pattern measured at the first level (Lin: annotated fig. 22, top level circle in L1) and the impurity concentration of the source/drain pattern measured at the second level (Lin: bottom level square in L2) is around 1%~8% (Lin: Based on L2 of 1-5×10^21 atoms/cm3 and L1 of 5-10×10^20 atoms/cm3, which can be calculated as difference between 2%~10% and 1%~2% doping; para. 0048), which overlaps in a range from 0.5 at% to 2 at%. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the impurity concentration of the source/drain pattern measured at the first level and the impurity concentration of the source/drain pattern measured at the second level from 1%~8% to from 0.5 at% to 2 at%. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 14 , Choi in view of Lin further teaches the semiconductor device of claim 11, wherein a length of the uppermost semiconductor pattern (Choi: fig. 2A, top width of N3) of the plurality of semiconductor patterns is greater than a length of the lowermost semiconductor pattern (Choi: top width of N1) of the plurality of semiconductor patterns. Regarding claim 15 , Choi in view of Lin further teaches the semiconductor device of claim 11, wherein the source/drain pattern (Choi: fig. 2A, 130) further comprises a buffer layer (Choi: outer blocking layer 132; para. 0039) and a main layer (Choi: inner blocking layer 134, main body layer 136; para. 0039) on the buffer layer (132), and wherein the main layer (Choi: 134, 136) extends from the first level (top level) to the second level (bottom level) . 07-21-aia AIA Claim s 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220045103) in view of Lin . Regarding claim 16 , Kim teaches a semiconductor device (Abstract), comprising: a substrate (fig. 2B, support substrate 100; para. 0029) comprising an n-type metal-oxide-semiconductor (MOS) field effect transistor (FET) (NMOSFET) region (NMOSFET region NR; para. 0031); an active pattern (second semiconductor pattern 102b; para. 0032) on the NMOSFET region (NR); a channel pattern (second channel structures CH2; para. 0032) on the active pattern (102b), the channel pattern (CH2) comprising a plurality of semiconductor patterns (first channel pattern SP1, second channel pattern SP2, third channel pattern SP3; para. 0032) stacked and spaced apart, the plurality of semiconductor patterns comprising a first semiconductor pattern (SP1), a second semiconductor pattern (SP2) adjacent to the first semiconductor pattern (SP1), and an uppermost semiconductor pattern (SP3); a source/drain pattern (first and second source/drain patterns SD1, SD2; para. 0034) on the active pattern (102b) and comprising an impurity (dopant; para. 0034); a gate electrode (gate electrode GE; para. 0044) on the channel pattern (CH2), the gate electrode (GE) comprising an inner electrode (second portion PO2; para. 0038) between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2), and an outer electrode (fourth portion PO4; para. 0038) on the uppermost semiconductor pattern (SP3); a gate insulating layer (gate insulating layer GI; para. 0040) between the inner electrode (PO2) and the source/drain pattern (SD2); a gate spacer (gate spacers GS; para. 0043) on a side surface of the outer electrode (PO4); a gate capping pattern (gate capping pattern GP; para. 0044) on a top surface of the outer electrode (GE); an interlayer insulating layer (second interlayer insulating layers 120; para. 0044) on the gate capping pattern (GP) and the source/drain pattern (SD2); a gate contact (fig. 2D, gate contact GC; para. 0050) connected to the gate electrode (GE) and penetrating the interlayer insulating layer (120) and the gate capping pattern (GP); an active contact (fig. 2C, source/drain contacts AC; para. 0050) connected to the source/drain pattern (SD2) and penetrating the interlayer insulating layer (120); and a first metal layer (first metal layer M1; para. 0052) on the interlayer insulating layer (120), wherein the first metal layer (M1) comprises first interconnection lines (lower vias VI1; para. 0053) respectively connected to the gate contact (GC) and the active contact (AC), wherein a length of the first semiconductor pattern (fig. 2D, width of SP1) is greater than a length of the second semiconductor pattern (width of SP2). Kim fails to explicitly teach an impurity concentration of the source/drain pattern is a first atomic fraction at a first level corresponding to the first semiconductor pattern, wherein the impurity concentration of the source/drain pattern is a second atomic fraction at a second level corresponding to the second semiconductor pattern, and wherein the first atomic fraction is greater than the second atomic fraction. However, Lin teaches an impurity concentration (Lin: fig. 21, annotated fig. 22, dopant of layers L1, L2; para. 0048) of the source/drain pattern (Lin: source/drain layer 2102, 2104; para. 0060, similar to SD2 of Kim) is a first atomic fraction (Lin: doping in L2) at a first level (Lin: bottom level square in L2) corresponding to the first semiconductor pattern (Lin: bottom layers 308; para. 0022, similar to SP1 of Kim), wherein the impurity concentration of the source/drain pattern is a second atomic fraction (Lin: doping in L1) at a second level (Lin: middle level triangle in L1) corresponding to the second semiconductor pattern (Lin: middle 308, similar to SP2 of Kim), and wherein the first atomic fraction (Lin: doping in L2) is greater (Lin: L2 has higher dopant concentration than L1; para. 0048) than the second atomic fraction (Lin: doping in L1)). Lin and Kim are considered to be analogous to the claimed invention because they are in the same field of transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first atomic fraction is greater than the second atomic fraction as taught by Lin. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Regarding claim 17 , Kim in view of Lin further teaches the semiconductor device of claim 16, wherein the gate insulating layer (Kim: fig. 3A, GI) directly contacts the source/drain pattern (Kim: SD1). Regarding claim 18 , Kim in view of Lin further teaches the semiconductor device of claim 16, wherein the impurity (Lin: dopant) is at least one of phosphorus, arsenic, and antimony (Lin: phosphorous (P); para. 0045). Regarding claim 17 , Kim in view of Lin further teaches the semiconductor device of claim 16 including the first atomic fraction (Lin: doping in L2). Kim in view of Lin as applied to claim 16 above fails to explicitly teach a difference between the first atomic fraction and the second atomic fraction is in a range from 0.5 at% to 2 at%. However, Lin teaches a difference between the first atomic fraction (Lin: annotated fig. 22, doping in bottom level square in L2) and the second atomic fraction (Lin: doping in middle level triangle in L1) is around 1%~8% (Lin: Based on L2 of 1-5×10^21 atoms/cm3 and L1 of 5-10×10^20 atoms/cm3, which can be calculated as difference between 2%~10% and 1%~2% doping; para. 0048), which overlaps in a range from 0.5 at% to 2 at%. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the difference between the first atomic fraction and the second atomic fraction from 1%~8% to from 0.5 at% to 2 at%. Doing so would realize dopant gradient within the source/drain epitaxial features to improve source/drain features (Lin: para. 0017). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 20 , Kim in view of Lin further teaches the semiconductor device of claim 16, wherein the first level (Kim: fig. 2B, SP1) is lower than the second level (Kim: SP2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHIJUN XU/Examiner, Art Unit 2818 /BRIAN TURNER/Examiner, Art Unit 2818 Application/Control Number: 18/609,885 Page 2 Art Unit: 2818 Application/Control Number: 18/609,885 Page 3 Art Unit: 2818 Application/Control Number: 18/609,885 Page 4 Art Unit: 2818 Application/Control Number: 18/609,885 Page 5 Art Unit: 2818 Application/Control Number: 18/609,885 Page 6 Art Unit: 2818 Application/Control Number: 18/609,885 Page 7 Art Unit: 2818 Application/Control Number: 18/609,885 Page 8 Art Unit: 2818 Application/Control Number: 18/609,885 Page 9 Art Unit: 2818 Application/Control Number: 18/609,885 Page 10 Art Unit: 2818 Application/Control Number: 18/609,885 Page 11 Art Unit: 2818 Application/Control Number: 18/609,885 Page 12 Art Unit: 2818 Application/Control Number: 18/609,885 Page 13 Art Unit: 2818 Application/Control Number: 18/609,885 Page 14 Art Unit: 2818 Application/Control Number: 18/609,885 Page 15 Art Unit: 2818 Application/Control Number: 18/609,885 Page 16 Art Unit: 2818 Application/Control Number: 18/609,885 Page 17 Art Unit: 2818 Application/Control Number: 18/609,885 Page 18 Art Unit: 2818
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