Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Replacement drawing sheets for figure 5 have been filed by applicant and are only adjusting numerals of the originally filed drawings. The drawings were received on 9/3/2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-2, 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210134747 A1) in view of Ren (US 20160379819 A1).
Regarding claim 1, Kuang discloses a semiconductor package (Fig. 5) comprising:
a first semiconductor die (1) including a first substrate (102), a first bonding layer (122) on the first substrate (indirectly “on”), and a first conductive pattern (134) passing through the first bonding layer (completely through);
a second semiconductor die (2) disposed on (directly “on”) the first semiconductor die, the second semiconductor die including a second substrate (202), a second bonding layer (222) under the second substrate (indirectly “under”), and a second conductive pattern (234/232a) passing through the second bonding layer (completely through); and
a silicon oxide layer (124/224; [0022]: “silicon oxide”. Note: this layer ultimately becomes a single layer from the bonding process, [0032]: “dielectric-to-dielectric bonding”) interposed between (sandwiched “between”) the first semiconductor die and the second semiconductor die,
wherein at least one pore is disposed in the silicon oxide layer,
wherein the at least one pore has a height of 1 Å to 2 nm, and
wherein the at least one pore horizontally overlaps both the first conductive pattern and the second conductive pattern.
Illustrated below is a marked and annotated figure of Fig. 5 of Yang.
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Yang separately teaches “at least one pore” and “silicon oxide” ([0022]: “silicon oxide…porous”), but fails to teach these features combined for the same “layer”. Thus, Yang fails to teach the claimed layer configuration:
“wherein at least one pore is disposed in the silicon oxide layer,
wherein the at least one pore has a height of 1 Å to 2 nm, and
wherein the at least one pore horizontally overlaps both the first conductive pattern and the second conductive pattern.”
Ren discloses a layer configuration:
wherein at least one pore ([0023]: “porous”) is disposed in the silicon oxide layer ([0023]: “a silicon oxide”),
wherein the at least one pore has a height of 1 Å to 2 nm ([0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”), and
wherein the at least one pore horizontally overlaps (Note: the pores are inclusive within the material, and thus necessarily “horizontally overlaps” any structure “passing through” the “layer”) both the first conductive pattern and the second conductive pattern (Note: a single conductive pattern [0023]: “metallic material” is relied upon here, and corresponds to each of the conductive patterns of Yang.).
Modifying the “silicon oxide layer” (of Yang) by substituting it with the “silicon oxide layer” of Ren (i.e., a combination of “at least one pore” with “silicon oxide”) would arrive at the claimed “layer” configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Yang teaches a porous low-k dielectric material may be used in place of the cited silicon oxide layer ([0022]: “porous low-k dielectric material”); and 2) Ren teaches the silicon oxide layer is a porous low-k dielectric material ([0023]: “the porous low-k dielectric layer is…a silicon oxide”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed silicon oxide layer “pore” configuration because it is a known suitable substitution encompassed within the teachings of the prior art. MPEP 2143 (I)(B).
Regarding claim 2, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5), wherein the at least one pore has a width of 1 nm to 100 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 5, Yang in vies of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5), wherein all of the pores are spaced apart (Note: the pores and the conductive patterns are each separate and distinct structures. Accordingly, these features must necessarily be “spaced apart” by at least some amount. MPEP 2111) from the first conductive pattern and the second conductive pattern.
Regarding claim 6, Yang in view of Ren discloses the semiconductor package of claim 5 (Yang: Fig. 5),
wherein a width of the first conductive pattern (See annotated figure for width designation) is smaller than (“smaller than” because the 1st width is fully within the 2nd width. See dashed reference lines for the difference.) a width of the second conductive pattern (See annotated figure for width designation),
wherein the silicon oxide layer is in contact (at least indirect “contact” in some direction) with a bottom surface and a lower sidewall of the second conductive pattern, and
wherein the silicon oxide layer is in contact (at least indirect “contact” in some direction) with an upper sidewall of the first conductive pattern.
Regarding claim 7, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5),
wherein the silicon oxide layer has a first thickness (Fig. 4: T1), and
wherein at least one of the first bonding layer or the second bonding layer has a second thickness (T3) greater than the first thickness (“greater” because [0028]: “thickness T1…50 to 10000 angstroms” and “thickness T3 5 to 1000 angstroms” includes a plurality of values capable of meeting the claim, and there is no other required relation between these thicknesses).
Regarding claim 8, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5), wherein all of the pores are spaced apart (Note: the pores and the bonding layers are each separate and distinct structures. Accordingly, these features must necessarily be “spaced apart” by at least some amount. MPEP 2111) from the first bonding layer and the second bonding layer.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lu (US 20240393653 A1).
Regarding independent claim 16, Yang discloses a semiconductor package (Fig. 5) comprising:
a first semiconductor die (1) including a first substrate (102), a first bonding layer (122) on the first substrate (indirectly “on”), and a first conductive pattern (134) passing through the first bonding layer (completely through);
a second semiconductor die (2) disposed on (directly “on”) the first semiconductor die and partially exposing an upper surface of the first semiconductor die, the second semiconductor die including a second substrate (202), a second bonding layer (222) under the second substrate (indirectly “under”), and a second conductive pattern (234/232a) extending through the second bonding layer (completely through);
a silicon oxide layer (124/224; [0022]: “silicon oxide”. Note: this layer ultimately becomes a single layer from the bonding process, [0032]: “dielectric-to-dielectric bonding”) interposed between (sandwiched “between”) the first bonding layer and the second bonding layer, the silicon oxide layer being in contact (at least indirect “contact” in some direction) with a plurality of side surfaces of the first conductive pattern and the second conductive pattern;
a mold layer covering a side surface of the second semiconductor die and an upper surface of the first semiconductor die; and
an external connection terminal bonded to a lower surface of the first semiconductor die,
wherein the first bonding layer and the second bonding layer comprise silicon carbon nitride (SiCN) ([0024]: “SiCN”),
wherein the first bonding layer or the second bonding layer has a first thickness (Fig. 4: T3),
wherein the silicon oxide layer has a second thickness (T1) smaller than the first thickness (“smaller” because [0028]: “thickness T3 5 to 1000 angstroms” and “thickness T1…50 to 10000 angstroms” includes a plurality of values capable of meeting the claim, and there is no other required relation between these thicknesses),
wherein the silicon oxide layer is composed of a single layer of SiO2 ([0022]: “silicon oxide”. Note: this layer ultimately becomes a single layer from the bonding process, [0032]: “dielectric-to-dielectric bonding”), and
wherein the silicon oxide layer horizontally overlaps (the layer formed by 124/224 at least partially “overlaps”) both the first conductive pattern and the second conductive pattern.
Yang teaches the first and second semiconductor dies, but these teachings lack specific details regarding the dimensional configurations of these chips. Thus, Yang fails to teach the claimed chip configuration
“a second semiconductor die disposed on the first semiconductor die and partially exposing an upper surface of the first semiconductor die, the second semiconductor die including a second substrate, a second bonding layer under the second substrate, and a second conductive pattern extending through the second bonding layer;
a silicon oxide layer interposed between the first bonding layer and the second bonding layer, the silicon oxide layer being in contact with a plurality of side surfaces of the first conductive pattern and the second conductive pattern;
a mold layer covering a side surface of the second semiconductor die and an upper surface of the first semiconductor die; and
an external connection terminal bonded to a lower surface of the first semiconductor die,”
Lu discloses a semiconductor package (Fig. 8) comprising:
a second semiconductor die (20a) disposed on (directly “on”) the first semiconductor die (210) and partially exposing an upper surface of the first semiconductor die (See annotated figure for surface designation), the second semiconductor die including a second substrate (Fig. 6B: 170), a second bonding layer under the second substrate, and a second conductive pattern (Fig. 6B: 328) extending through the second bonding layer;
a silicon oxide layer (Fig. 6B: 226/326; [0095]: “bonding layer…silicon oxide”) interposed between the first bonding layer and the second bonding layer, the silicon oxide layer being in contact (direct contact) with a plurality of side surfaces of the first conductive pattern (Fig. 6B: 228) and the second conductive pattern;
a mold layer (Fig. 8: 22) covering a side surface of the second semiconductor die (See annotated figure for surface designation) and an upper surface of the first semiconductor die (See annotated figure for surface designation); and
an external connection terminal (238/236) bonded to a lower surface of the first semiconductor die
Modifying the package of Yang by incorporating the die and mold configurations of Lu would arrive at the claimed package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation semiconductor dies are directly bonded by the conductive patterns and the silicon oxide layer. A person of ordinary skill in the art before the effective filing date would have been motivated to combine the die bonding configuration of Yang with the die and mold dimensional configuration of Lu to arrive at a functional package (of Lu) with an improved bond between the dies (Yang: [0036]: “Device failure due to metal diffusion may be prevented. Furthermore, bonding strength of the bonded semiconductor structure may also be improved”). Therefore, it would have been obvious to have the claimed die and mold configuration because it would enable a functional package with improved an improved die bond. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 8 of Lu.
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Regarding claim 19, Yang in view of Lu discloses the semiconductor package of claim 16 (Yang: Fig. 5),
wherein a width of the first conductive pattern (See annotated figure for width designation) smaller than (“smaller than” because the 1st width is fully within the 2nd width. See dashed reference lines for the difference.) a width of the second conductive pattern (See annotated figure for width designation),
wherein the silicon oxide layer is in contact (at least indirect “contact” in some direction) with a bottom surface and a lower sidewall of the second conductive pattern, and
wherein the silicon oxide layer is in contact (at least indirect “contact” in some direction) with an upper sidewall of the first conductive pattern.
Claims 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang and Lu as applied to claim 16 above, and further in view of Yagihashi (US 20100040893 A1).
Regarding claim 17, Yang in view of Lu discloses the semiconductor package of claim 16, but only separately teaches “pores” and “SiO2” ([0022]: “silicon oxide…porous”), and therefor fails to teach these features combined for the same “layer”. Thus, Yang in view of Lu fails to teach the claimed layer configuration: “wherein pores are disposed in the silicon oxide layer and each of the pores has a height of 1 Å to 2 nm”.
Yagihashi discloses a layer configuration: wherein pores ([0027]: “pores”) are disposed in the silicon oxide layer ([0027]: “silicon oxide base”) and each of the pores has a height of 1 Å to 2 nm ([0027]: “a radius of about 1 to 10 nm…up to 1 nm” overlaps the claimed range).
Modifying the “silicon oxide layer” (of Yang) by including “pores” in the same way as Yagihashi would arrive at the claimed “pores” configuration. A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the “silicon oxide layer” is used to bond dies (Yang: [0032]: “dielectric-to-dielectric bonding”; Yagihashi: [0027]: “the substrates can be joined together”). Yagihashi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include pores in that it would improve die bonding characteristics ([0027]: “without a peeling problem”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed “pores” configuration because it would improve die bonding characteristics. MPEP 2143 (I)(G).
Regarding claim 18, Yang in view of Lu discloses the semiconductor package of claim 16, but only separately teaches “pores” and “SiO2” ([0022]: “silicon oxide…porous”), and therefor fails to teach these features combined for the same “layer”. Thus, Yang in view of Lu fails to teach the claimed layer configuration: “wherein pores are disposed in the silicon oxide layer and each of the pores has a width of 1 nm to 100 nm”.
Yagihashi discloses a layer configuration: wherein pores ([0027]: “pores”) are disposed in the silicon oxide layer ([0027]: “silicon oxide base”) and each of the pores has a width of 1 nm to 100 nm ([0027]: “a radius of about 1 to 10 nm…up to 1 nm” overlaps the claimed range).
Modifying the “silicon oxide layer” (of Yang) by including “pores” in the same way as Yagihashi would arrive at the claimed “pores” configuration. A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the “silicon oxide layer” is used to bond dies (Yang: [0032]: “dielectric-to-dielectric bonding”; Yagihashi: [0027]: “the substrates can be joined together”). Yagihashi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include pores in that it would improve die bonding characteristics ([0027]: “without a peeling problem”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed “pores” configuration because it would improve die bonding characteristics. MPEP 2143 (I)(G).
Regarding claim 20, Yang in view of Lu discloses the semiconductor package of claim 16, but only separately teaches “pores” and “SiO2” ([0022]: “silicon oxide…porous”), and therefor fails to teach these features combined for the same “layer”. Thus, Yang in view of Lu fails to teach the claimed layer configuration:
“wherein pores are disposed in the silicon oxide layer, and
wherein all of the pores are spaced apart from both the first bonding layer and the second bonding layer.”
Yagihashi discloses a layer configuration: wherein pores ([0027]: “pores”) are disposed in the silicon oxide layer ([0027]: “silicon oxide base”).
Modifying the “silicon oxide layer” (of Yang) by including “pores” in the same way as Yagihashi would arrive at the claimed “pores” configuration because:
(Yang: Fig. 5) wherein all of the pores are spaced apart (Note: the pores and the bonding layers are each separate and distinct structures. Accordingly, these features must necessarily be “spaced apart” by at least some amount. MPEP 2111) from both the first bonding layer and the second bonding layer.”
A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the “silicon oxide layer” is used to bond dies (Yang: [0032]: “dielectric-to-dielectric bonding”; Yagihashi: [0027]: “the substrates can be joined together”). Yagihashi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include pores in that it would improve die bonding characteristics ([0027]: “without a peeling problem”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed “pores” configuration because it would improve die bonding characteristics. MPEP 2143 (I)(G).
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 3-4 is the inclusion of the limitation “wherein the first plurality of SiCN grains and the second plurality of SiCN grains have t-SiCN crystal structures” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “SiCN grains” and “t-SiCN crystal structures” in combination with all other limitations in claims 3 and 1. The claimed crystal structure “t-SiCN” was found elsewhere in the prior art but it was not found to anticipate the claim, and incorporating it in the way claimed was not found obvious.
The primary reason for the allowable subject matter of claims 9-15 is the inclusion of the limitation “wherein the plurality of SiCN grains have t-SiCN crystal structures” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “SiCN grains” and “t-SiCN crystal structures” in combination with all other limitations in claim 9. The claimed crystal structure “t-SiCN” was found elsewhere in the prior art but it was not found to anticipate the claim, and incorporating it in the way claimed was not found obvious.
Response to Arguments
Applicant's arguments filed 9/3/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to claim 1 that “Ren’s SiCOH dielectric layer is not a silicon oxide layer as claimed”. Remarks at pg. 11.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The claim requires “silicon oxide”, and Applicant’s arguments appear to be directed to a particular material+layer configuration (Disclosure: Fig. 2). Ren teaches a SiCOH which is a layer of an oxide of silicon, and is thus “silicon oxide”; and this material and layer configuration is within the breadth of the claim as written.
Applicant argues:
Applicant argues with respect to amended claim 1 that “neither Yang nor Ren disclose, suggest, or render obvious “wherein at least one pore […]” as recited by amended claim 1”. Remarks at pg. 11.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The claim reasonably includes pore configurations beyond the specific contended configuration of Applicant’s disclosure. The rejection is maintained substantially the same as before, with adjustments to citations and clarifying remarks as necessitated by claim amendment, and to promote clarity of the record.
Applicant argues:
Applicant argues with respect to amended claims 3 and 9 that “Onuma does not describe or suggest “wherein the plurality of SiCN grains have t-SiCN crystal structures” as in amended claims 3 and 9”. Remarks at pg. 12.
Examiner’s reply:
Applicant’s arguments, see pg. 12, filed 9/3/2026, with respect to amended claim 3 have been fully considered and are persuasive. The rejection of claim 3 has been withdrawn.
Applicant argues:
Applicant argues with respect to amended claim 16 that “Yang describes a double layer of dielectric material”. Remarks at pg. 13.
Examiner’s reply:
Applicant's arguments filed 9/3/2026 have been fully considered but they are not persuasive. The examiner is interpreting in the instant Office action the contended “double layer” as a “single layer” based on the ultimate configuration of these layers, which is an inter-diffused bonding of two similar layers, ultimately arriving at a single integral layer. MPEP 2111.
Applicant argues:
Applicant argues with respect to amended claims 6, 13, and 19 that “Yang’s dielectric layer 124, however, is not “in contact with […] a width […] is smaller […]””. Remarks at pg. 14.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest reasonable interpretation. “contact” as claimed reasonably encompasses direct or indirect contact. Accordingly, the rejection is maintained in substantially the same way as before, with adjusted citations and remarks as necessitated by claim amendment, and to promote clarity of the record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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