Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 (and dependent claim 4 dependent therefrom) is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, “a height of the at least one pore” in line 5 is unclear whether it is referring to the same height recited in claim 1 or some other height. For the sake of compact prosecution, claim 3 is interpreted in the instant Office action as follows: “a height of the at least one pore” in line 5 is equivalent to “the height of the at least one pore”. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-2, 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210134747 A1) in view of Ren (US 20160379819 A1).
Regarding claim 1, Yang discloses a semiconductor package (Fig. 5) comprising:
a first semiconductor die (1) including a first substrate (102) and a first bonding layer (122), the first bonding layer being on (indirectly “on”) the first substrate;
a second semiconductor die (2) disposed on (directly “on”) the first semiconductor die, the second semiconductor die including a second substrate (202) and a second bonding layer (222), the second bonding layer being under (indirectly “under”) the second substrate; and
a silicon oxide layer (124/224; [0022]: “silicon oxide”) interposed between the first semiconductor die and the second semiconductor die,
wherein at least one pore is disposed in the silicon oxide layer, and
wherein the at least one pore has a height of 1 Å to 2 nm.
Illustrated below is a marked and annotated figure of Fig. 5 of Yang.
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Yang teaches the silicon oxide layer but fails to teach the claimed configuration:
“wherein at least one pore is disposed in the silicon oxide layer, and
wherein the at least one pore has a height of 1 Å to 2 nm”
Ren discloses a silicon oxide layer ([0023]: “a silicon oxide”)
wherein at least one pore ([0023]: “porous”) is disposed in the silicon oxide layer, and
wherein the at least one pore has a height of 1 Å to 2 nm ([0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Modifying the silicon oxide layer of Yang by substituting it with the silicon oxide layer of Ren would arrive at the claimed layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Yang teaches a porous low-k dielectric material may be used in place of the cited silicon oxide layer ([0022]: “porous low-k dielectric material”); and 2) Ren teaches the silicon oxide layer is a porous low-k dielectric material ([0023]: “the porous low-k dielectric layer is…a silicon oxide”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed silicon oxide layer pore configuration because it is a known suitable substitution encompassed within the teachings of the prior art. MPEP 2143 (I)(B).
Regarding claim 2, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5), wherein the at least one pore has a width of 1 nm to 100 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 5, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5),
wherein the first semiconductor die includes a first conductive pattern (134) disposed on (indirectly “on”) the first substrate, the first conductive pattern extending through (completely through) the first bonding layer,
wherein the second semiconductor die includes a second conductive pattern (234/232a) disposed under (indirectly “under”) the second substrate, the second conductive pattern extending through (completely through) the second bonding layer, the second conductive pattern being in contact (direct contact) with the first conductive pattern, and
wherein the at least one pore is spaced apart from the first conductive pattern and the second conductive pattern (the pore is within oxide layer 124/224 which is separate and distinct from conductive patterns 134/234/232a, thus at least some of the pore must necessarily be spaced apart from at least some of the conductive patterns).
Regarding claim 6, Yang in view of Ren discloses the semiconductor package of claim 5 (Yang: Fig. 5), wherein a width of the first conductive pattern (See annotated figure for width designation) is different (See dashed reference lines for the difference) from a width of the second conductive pattern (See annotated figure for width designation).
Regarding claim 7, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5),
wherein the silicon oxide layer has a first thickness (Fig. 4: T1), and
Wherein at least one of the first bonding layer or the second bonding layer has a second thickness (T3) greater than the first thickness (“greater” because [0028]: “thickness T1…50 to 10000 angstroms” and “thickness T3 5 to 1000 angstroms” includes a plurality of values capable of meeting the claim, and there is no other required relation between these thicknesses).
Regarding claim 8, Yang in view of Ren discloses the semiconductor package of claim 1 (Yang: Fig. 5), wherein the at least one pore is spaced apart from the first bonding layer and the second bonding layer (the pore is within oxide layer 124/224 which is separate and distinct from bonding layers 122/222, thus at least some of the pore must necessarily be spaced apart from at least some of the bonding layers).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ren as applied to claim 1 above, and further in view of Onuma (US 20230109233 A1).
Regarding claim 3 as noted in the 112(b) rejection, Yang in view of Ren discloses the semiconductor package of claim 1,
wherein the first bonding layer includes a first plurality of silicon carbon nitride (SiCN) ([0024]: “SiCN”) grains and the second bonding layer includes a second plurality of SiCN ([0024]: “SiCN”) grains, and
wherein an average size of the first plurality of SiCN grains or an average size of the second plurality of SiCN grains is greater than the height of the at least one pore (previously cited, Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Yang in view of Ren generically teaches the first and second bonding layers include SiCN, but fails to teach specific characteristics of SiCN, and thus fails to teach:
“wherein the first bonding layer includes a first plurality of silicon carbon nitride (SiCN) grains and the second bonding layer includes a second plurality of SiCN grains, and
wherein an average size of the first plurality of SiCN grains or an average size of the second plurality of SiCN grains is greater than the height of the at least one pore.”
Onuma discloses a SiCN layer ([0061]: “a thin film composed of an aggregation of particles”) with plurality of SiCN grains ([0061]: “nano particles…SiCN”), and teaches these grains have an average grain size (Onuma: [0061]: “an average diameter of several nanometers (nm) to several hundred nanometers”) larger than the pores of Yang in view of Ren (Ren: [0023]: “diameters in the range of about 0.5 nanometers to about 20 nanometers”). Thus, the claimed SiCN grains and relation to the pore configuration is a characteristic (SiCN grain size taught by Onuma) of the composition disclosed by Yang in view of Ren (the pores of Ren; the SiCN composition of Yang). Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it is a known characteristic of an otherwise similar composition. MPEP 2112 (III).
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ren and Onuma.
Regarding independent claim 9, Yang discloses a semiconductor package (Fig. 5) comprising:
a first semiconductor die (1) including a first substrate (102) and a first bonding layer (122), the first bonding layer being on (indirectly “on”) the first substrate;
a second semiconductor die (2) disposed on (directly “on”) the first semiconductor die, the second semiconductor die including a second substrate (202) and a second bonding layer (222), the second bonding layer being under (indirectly “under”) the second substrate; and
a silicon oxide layer (124/224; [0022]: “silicon oxide”. Note: [0030] relates the die 2 configurations to the die 1 configurations; thus, the die 1 citations are relied upon for teaching substantially similar features also found in die 2.) interposed between the first semiconductor die and the second semiconductor die,
wherein at least one pore is disposed in the silicon oxide layer,
wherein the first bonding layer and the second bonding layer include a plurality of silicon carbon nitride (SiCN) grains ([0024]: “SiCN”. Note: there must necessarily be at least some grain in each layer, thus “grains” within the scope of this limitation), and
wherein a height of the at least one pore is smaller than an average size of the plurality of SiCN grains.
Yang teaches the silicon oxide layer but fails to teach the claimed configuration:
“wherein at least one pore is disposed in the silicon oxide layer
Ren discloses a silicon oxide layer ([0023]: “a silicon oxide”)
wherein at least one pore ([0023]: “porous”) is disposed in the silicon oxide layer.
Modifying the silicon oxide layer of Yang by substituting it with the silicon oxide layer of Ren would arrive at the claimed layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Yang teaches a porous low-k dielectric material may be used in place of the cited silicon oxide layer ([0022]: “porous low-k dielectric material”); and 2) Ren teaches the silicon oxide layer is a porous low-k dielectric material ([0023]: “the porous low-k dielectric layer is…a silicon oxide”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed silicon oxide layer pore configuration because it is a known suitable substitution encompassed within the teachings of the prior art. MPEP 2143 (I)(B).
Yang in view of Ren generically teaches the plurality of SiCN grains, but fails to teach specific characteristics of SiCN, and thus fails to teach:
“wherein a height of the at least one pore is smaller than an average size of the plurality of SiCN grains.”
Onuma discloses a plurality of SiCN grains ([0061]: “nano particles…SiCN”), and teaches these grains have an average grain size (Onuma: [0061]: “an average diameter of several nanometers (nm) to several hundred nanometers”) larger than the pores of Yang in view of Ren (Ren: [0023]: “diameters in the range of about 0.5 nanometers to about 20 nanometers”). Thus, the claimed SiCN grains and relation to the pore configuration is a characteristic (SiCN grain size taught by Onuma) of the composition disclosed by Yang in view of Ren (the pores of Ren; the SiCN composition of Yang). Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it is a known characteristic of an otherwise similar composition. MPEP 2112 (III).
Regarding claim 10, Yang in view of Ren and Onuma discloses the semiconductor package of claim 9 (Yang: Fig. 5), wherein the at least one pore has a height of 1 Å to 2 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 11, Yang in view of Ren and Onuma discloses the semiconductor package of claim 9 (Yang: Fig. 5), wherein the at least one pore has a width of 1 nm to 100 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 12, Yang in view of Ren and Onuma discloses the semiconductor package of claim 9 (Yang: Fig. 5),
wherein the first semiconductor die includes a first conductive pattern (134) disposed on (indirectly “on”) the first substrate, the first conductive pattern extending through (completely through) the first bonding layer,
wherein the second semiconductor die includes a second conductive pattern (234/232a) disposed under (indirectly “under”) the second substrate, the second conductive pattern extending through (completely through) the second bonding layer, the second conductive pattern being in contact (direct contact) with the first conductive pattern, and
wherein the at least one pore is spaced apart from the first conductive pattern and the second conductive pattern (the pore is within oxide layer 124/224 which is separate and distinct from conductive patterns 134/234/232a, thus at least some of the pore must necessarily be spaced apart from at least some of the conductive patterns).
Regarding claim 13, Yang in view of Ren and Onuma discloses the semiconductor package of claim 12 (Yang: Fig. 5), wherein a width of the first conductive pattern (See annotated figure for width designation) is different (See dashed reference lines for the difference) from a width of the second conductive pattern (See annotated figure for width designation).
Regarding claim 14, Yang in view of Ren and Onuma discloses the semiconductor package of claim 9 (Yang: Fig. 5),
wherein the silicon oxide layer has a first thickness (Fig. 4: T1), and
wherein at least one of the first bonding layer or the second bonding layer has a second thickness (T3) greater than the first thickness (“greater” because [0028]: “thickness T1…50 to 10000 angstroms” and “thickness T3 5 to 1000 angstroms” includes a plurality of values capable of meeting the claim, and there is no other required relation between these thicknesses).
Regarding claim 15, Yang in view of Ren and Onuma discloses the semiconductor package of claim 9 (Yang: Fig. 5), wherein the at least one pore is spaced apart from the first bonding layer and the second bonding layer (the pore is within oxide layer 124/224 which is separate and distinct from bonding layers 122/222, thus at least some of the pore must necessarily be spaced apart from at least some of the bonding layers).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lu (US 20240393653 A1) and Ren.
Regarding independent claim 16, Yang discloses a semiconductor package (Fig. 5) comprising:
a first semiconductor die (1) including a first substrate (102), a first bonding layer (122) on (indirectly “on”) the first substrate, and a first conductive pattern (134) passing through (completely through) the first bonding layer;
a second semiconductor die (2) disposed on (directly “on”) the first semiconductor die and partially exposing an upper surface of the first semiconductor die, the second semiconductor die including a second substrate (202), a second bonding layer (222) under (indirectly “under”) the second substrate, and a second conductive pattern (234/232a) extending through the second bonding layer (completely through);
a silicon oxide layer (124/224; [0022]: “silicon oxide”) interposed between the first bonding layer and the second bonding layer, the silicon oxide layer being in contact (at least indirect “contact”) with a plurality of side surfaces of the first conductive pattern and the second conductive pattern;
a mold layer covering a side surface of the second semiconductor die and an upper surface of the first semiconductor die; and
an external connection terminal bonded to a lower surface of the first semiconductor die,
wherein the first bonding layer and the second bonding layer comprise silicon carbon nitride (SiCN) ([0024]: “SiCN”),
wherein the first bonding layer or the second bonding layer has a first thickness (Fig. 4: T3),
wherein the silicon oxide layer has a second thickness (T1) smaller than the first thickness (“smaller” because [0028]: “thickness T3 5 to 1000 angstroms” and “thickness T1…50 to 10000 angstroms” includes a plurality of values capable of meeting the claim, and there is no other required relation between these thicknesses),
wherein at least one pore is disposed in the silicon oxide layer, and
wherein the at least one pore is spaced apart from the first conductive pattern and the second conductive pattern.
Yang teaches the first and second semiconductor dies, but these teachings lack specific details regarding the dimensional configurations of these chips. Thus, Yang fails to teach the claimed chip configuration
“a second semiconductor die disposed on the first semiconductor die and partially exposing an upper surface of the first semiconductor die, the second semiconductor die including a second substrate, a second bonding layer under the second substrate, and a second conductive pattern extending through the second bonding layer;
a silicon oxide layer interposed between the first bonding layer and the second bonding layer, the silicon oxide layer being in contact with a plurality of side surfaces of the first conductive pattern and the second conductive pattern;
a mold layer covering a side surface of the second semiconductor die and an upper surface of the first semiconductor die; and
an external connection terminal bonded to a lower surface of the first semiconductor die,”
Lu discloses a semiconductor package (Fig. 8) comprising:
a second semiconductor die (20a) disposed on (directly “on”) the first semiconductor die (210) and partially exposing an upper surface of the first semiconductor die (See annotated figure for surface designation), the second semiconductor die including a second substrate (Fig. 6B: 170), a second bonding layer under the second substrate, and a second conductive pattern (Fig. 6B: 328) extending through the second bonding layer;
a silicon oxide layer (Fig. 6B: 226/326; [0095]: “bonding layer…silicon oxide”) interposed between the first bonding layer and the second bonding layer, the silicon oxide layer being in contact (direct contact) with a plurality of side surfaces of the first conductive pattern (Fig. 6B: 228) and the second conductive pattern;
a mold layer (Fig. 8: 22) covering a side surface of the second semiconductor die (See annotated figure for surface designation) and an upper surface of the first semiconductor die (See annotated figure for surface designation); and
an external connection terminal (238/236) bonded to a lower surface of the first semiconductor die
Modifying the package of Yang by incorporating the die and mold configurations of Lu would arrive at the claimed package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation semiconductor dies are directly bonded by the conductive patterns and the silicon oxide layer. A person of ordinary skill in the art before the effective filing date would have been motivated to combine the die bonding configuration of Yang with the die and mold dimensional configuration of Lu to arrive at a functional package (of Lu) with an improved bond between the dies (Yang: [0036]: “Device failure due to metal diffusion may be prevented. Furthermore, bonding strength of the bonded semiconductor structure may also be improved”). Therefore, it would have been obvious to have the claimed die and mold configuration because it would enable a functional package with improved an improved die bond. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 8 of Lu.
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Yang in view of Lu teaches the silicon oxide layer but fails to teach the claimed configuration:
wherein at least one pore is disposed in the silicon oxide layer, and
wherein the at least one pore is spaced apart from the first conductive pattern and the second conductive pattern.
Ren discloses a silicon oxide layer ([0023]: “a silicon oxide”)
wherein at least one pore ([0023]: “porous”) is disposed in the silicon oxide layer
Modifying the silicon oxide layer of Yang in view of Lu by substituting it with the silicon oxide layer of Ren would arrive at the claimed layer configuration “wherein the at least one pore is spaced apart from the first conductive pattern and the second conductive pattern” because the pore would be within oxide layer 124/224 which is separate and distinct from conductive patterns 134/234/232a, thus at least some of the pore must necessarily be spaced apart from at least some of the conductive patterns. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Yang teaches a porous low-k dielectric material may be used in place of the cited silicon oxide layer ([0022]: “porous low-k dielectric material”); and 2) Ren teaches the silicon oxide layer is a porous low-k dielectric material ([0023]: “the porous low-k dielectric layer is…a silicon oxide”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed silicon oxide layer pore configuration because it is a known suitable substitution encompassed within the teachings of the prior art. MPEP 2143 (I)(B).
Regarding claim 17, Yang in view of Lu and Ren discloses the semiconductor package of claim 16 (Yang: Fig. 5), wherein the at least one pore has a height of 1 Å to 2 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 18, Yang in view of Lu and Ren discloses the semiconductor package of claim 16, wherein the at least one pore has a width of 1 nm to 100 nm (Ren: [0023]: “micropores having diameters in the range of about 0.5 nanometers to about 20 nanometers”).
Regarding claim 19, Yang in view of Lu and Ren discloses the semiconductor package of claim 16 (Yang: Fig. 5), wherein a width of the first conductive pattern (See annotated figure for width designation) is different (See dashed reference lines for the difference) from a width of the second conductive pattern (See annotated figure for width designation).
Regarding claim 20, Yang in view of Lu and Ren discloses the semiconductor package of claim 16 (Yang: Fig. 5), wherein the at least one pore is spaced apart from the first bonding layer or the second bonding layer (the pore is within oxide layer 124/224 which is separate and distinct from bonding layers 122/222, thus at least some of the pore must necessarily be spaced apart from at least some of the bonding layers).
Allowable Subject Matter
Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 4 is the inclusion of the limitation “wherein at least one of the first bonding layer or the second bonding layer includes a plurality of water molecules trapped between at least one of the first plurality of SiCN grains or the second plurality of SiCN grains, respectively” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “water molecules”, “trapped”, and “SiCN” in combination with all other limitations in claims 4, 3, and 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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