DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Invention I, Claims 1-16 and 19-20, in the reply filed on April 14, 2026 is acknowledged.
Applicant's election with traverse of Species 1 in the reply filed on November 17, 2025, is acknowledged. The traversal is on the ground(s) that FIGs. 16-19 show obvious variation of FIG. 2. This is not found persuasive because Applicant fails to admitted that the embodiments in FIGs. 16-18 are obvious variation of the Elected Species as shown in FIG. 2, where the stacked structure are aligned.
The requirement is still deemed proper and is therefore made FINAL.
Amendment filed April 14, 2026 is acknowledged. Claims 1-20 are pending. Non-elected Invention, claims 17-18 have been withdrawn from consideration. Applicant identified claims 1-16 and 19-20 are readable on the elected Invention I and Species 1.
Claim 3 recites: the semiconductor device according to claim 1, wherein in the plurality of second-conductivity-type regions included in a respective one of the plurality of second-conductivity-type voltage withstanding regions, misalignment of respective positions of the plurality of second-conductivity-type regions in a direction of a normal of the concentric circles is in a range from 0.05 m to 0.3 m.
Thus, claim 3 directs to non-elected Species.
Claims 5, 7, 9 and 11 dependent on claim 3.
Therefore, claims 3, 5, 7, 9 and 11 are effectively withdrawn from consideration.
Claim 4 recites: the semiconductor device according to claim 1, wherein among the plurality of second-conductivity-type regions, included in a respective one of the plurality of second-conductivity-type voltage withstanding regions, a width in a direction of a normal of the concentric circles of at least one of the plurality of second-conductivity-type regions is different from a width of other ones of the plurality of second-conductivity-type regions.
Thus, claim 4 directs to non-elected Species.
Therefore, claim 4 is effectively withdrawn from consideration.
Action on merits of the Elected Invention I, Species 1, Claims 1-2, 6, 8, 10, 12-16 and 19-20 claims follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/388,878, filed on July 29, 2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 19, 2024, May 01, 2024 and March 20, 2026 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SEMICONDUCTOR DEVICE HAVING DEVICE ELEMENT STRUCTURES WITH PN JUNCTION FORMED IN ACTIVE REGION AND VOLTAGE WITHSTANDING RINGS OF STACKED SECOND-CONDCUTIVITY-TYPE REGIONS FORMED IN PERIPHERY REGION SURROUNDING THE ACTIVE REGION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 15 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 15 recites: the semiconductor device according to claim 14, wherein the plurality of second-conductivity-type high-concentration regions includes:
a plurality of first high-concentration regions each facing a bottom of a respective one of the plurality of trenches in the depth direction, and
a plurality of second high-concentration regions each in contact with the second semiconductor region and separate from both the plurality of first high- concentration regions and the plurality of trenches.
The limitation of claim 15 is exactly the same as that of claim 14.
Therefore, claim 15 fails to further limit claim 14.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8, 10 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI et al. (US. Pub. No. 2018/0040688) in view of MIYAKE et al. (US. Pub. No. 2006/0300960).
With respect to claim 1, KOBAYASHI teaches a semiconductor device having an active region (102) through which a main current flows and a termination region (101) surrounding a periphery of the active region (102), as claimed, the semiconductor device including:
a semiconductor substrate containing a semiconductor (SiC) having a bandgap wider than a bandgap of silicon, the semiconductor substrate having a first main surface (top) and a second main surface (bottom) opposite to each other, the semiconductor substrate including a first-conductivity-type epitaxial layer that forms the first main surface of the semiconductor substrate;
a first semiconductor region (15) of a first conductivity type (n), provided in the semiconductor substrate;
a second semiconductor region (16) of a second conductivity type (p), selectivity provided in the semiconductor substrate in the active region (102), between the first main surface (top) of the semiconductor substrate and the first semiconductor region (15);
a device element structure formed in the semiconductor substrate in the active region (102), the device element structure having a pn junction between the second semiconductor region (16) and the first semiconductor region (15);
a first electrode (22) electrically connected to the second semiconductor region (16);
a second electrode (not shown) provided on the second main surface (bottom) of the semiconductor substrate; and
a plurality of second-conductivity-type voltage withstanding regions (8) each selectively provided in the semiconductor substrate in the termination region (101), between the first main surface (top) of the semiconductor substrate and the first semiconductor region (15), separate from the device element structure, the plurality of second-conductivity-type voltage withstanding regions (8) concentrically surrounding the periphery of the active region (102) to form concentric circles in a plan view of the semiconductor device, and being each provided separate from one another in a radial direction of the concentric circles,
wherein the device element structure includes:
a plurality of third semiconductor regions (17) of the first conductivity type (n), selectively provided in the semiconductor substrate, between the first main surface (front) of the semiconductor substrate and the second semiconductor region (16);
a plurality of trenches (19) penetrating through the plurality of third semiconductor regions (17) and the second semiconductor region (16), and reaching the first semiconductor region (15);
a plurality of gate electrodes (21) that are respectively provided in the plurality of trenches (19) via a respective one of a plurality of gate insulating films (19a); and
a plurality of fourth semiconductor regions (18) of the second conductivity type, selectively provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and the second semiconductor region (16), the plurality of fourth semiconductor regions (18) having an impurity concentration (p+) higher than an impurity concentration (p) of the second semiconductor region (16),
the first main surface (front) of the semiconductor substrate is a flat surface spanning both the active region (102) and the termination region (101),
the second semiconductor region (16) and the plurality of second-conductivity-type voltage withstanding regions (8) are impurity diffusion regions, each of which is selectively provided in a first portion (III) of the first-conductivity-type epitaxial layer,
the first semiconductor region (15) is a second portion (II) of the first-conductivity-type epitaxial layer excluding the first portion (III) of the first-conductivity-type epitaxial layer, the second portion (II) including regions, each of which is provided between a corresponding two of the plurality of second-conductivity-type voltage withstanding regions (8) that are adjacent to each other and reaches the first main surface (front) of the semiconductor substrate,
each of the plurality of second-conductivity-type voltage withstanding regions (88) is formed by a plurality of second-conductivity-type regions (p) in a depth direction orthogonal to the first main surface of the semiconductor substrate, and
at least one of the plurality of second-conductivity-type regions (8) included in a respective one of the plurality of second-conductivity-type voltage withstanding regions has an impunity concentration. (See FIGs. 3, 9).
Thus, KOBAYASHI ‘688 is shown to teach all the features of the claim with the exception of explicitly disclosing each of the plurality of second-conductivity-type voltage withstanding regions is formed by a plurality of second-conductivity-type regions that are stacked upon one another and at least one of the plurality of second-conductivity-type regions included in a respective one of the plurality of second-conductivity-type voltage withstanding regions has an impunity concentration that is equal to an impunity concentration of the second semiconductor region.
However, MIYAKE teaches a semiconductor device including:
a plurality of second-conductivity-type voltage withstanding regions (24) each selectively provided in a semiconductor substrate in the termination region, between the first main surface (top) of the semiconductor substrate and the first semiconductor region, separate from a device element structure, the plurality of second-conductivity-type voltage withstanding regions (24) concentrically surrounding the periphery of the active region to form concentric circles in a plan view of the semiconductor device, and being each provided separate from one another in a radial direction of the concentric circles,
each of the plurality of second-conductivity-type voltage withstanding regions (24) is formed by a plurality of second-conductivity-type regions (p) that are stacked upon one another in a depth direction (z) orthogonal to the first main surface of the semiconductor substrate, and
at least one of the plurality of second-conductivity-type regions (22) included in a respective one of the plurality of second-conductivity-type voltage withstanding regions (24) has an impunity concentration (p) that is equal to an impunity concentration (p) of the second semiconductor region (22). (See FIGs. 1-3).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the voltage withstanding regions of KOBAYASHI ‘688 comprising the plurality of second-conductivity-type regions that are stacked upon one another and at least one of the plurality of second-conductivity-type regions included in a respective one of the plurality of second-conductivity-type voltage withstanding regions has an impunity concentration that is equal to an impunity concentration of the second semiconductor region as taught by MIYAKE to enable operating with high breakdown voltage.
With respect to claim 2, the semiconductor device of KOBAYASHI further comprises a first-conductivity-type region (15b) selectively provided in the first semiconductor region (15) in the termination region (101), in contact with the plurality of second-conductivity-type voltage withstanding regions (8), the first-conductivity-type region (15b) having an impurity concentration higher than an impurity concentration of the first semiconductor region.
With respect to claim 6, in view of MIYAKE, among the plurality of second-conductivity-type regions (21/22/23) included in a respective one of the plurality of second-conductivity-type voltage withstanding regions (24), an impurity concentration of at least one of the plurality of second-conductivity-type regions differs from an impurity concentration of other ones of the plurality of second-conductivity-type regions.
With respect to claim 8, in view of MIYAKE, a number of the plurality of second-conductivity-type regions included in a respective one of the plurality of second-conductivity-type voltage withstanding regions (24) is at least three, and of the at least three of the plurality of second-conductivity-type regions, an impurity concentration of one near a center of the plurality of second-conductivity-type voltage withstanding regions (24) in the depth direction is lower than an impurity concentration of other ones of the at least three of the plurality of second-conductivity-type regions.
With respect to claim 10, the device element structure of KOBAYASHI further includes a plurality of second-conductivity-type high-concentration regions (3b), selectively provided in the first semiconductor region (15), and being each positioned closer to the second main surface of the semiconductor substrate than are bottoms of the plurality of trenches (19), the plurality of second-conductivity-type high-concentration regions (3b) having an impurity concentration higher than the impurity concentration of the second semiconductor region (16),
in view of MIYAKE, a number of the plurality of second-conductivity-type regions included in a respective one of the plurality of second-conductivity-type voltage withstanding regions (24) is three, and
of the three of the plurality of second-conductivity-type regions included in the respective one of the plurality of second-conductivity-type voltage withstanding regions (24):
a first second-conductivity-type region (21) that is closest to the first main surface of the semiconductor substrate has an impurity concentration that is the same as an impurity concentration of the plurality of fourth semiconductor regions (21), a second second-conductivity-type region (23) that is farthest from the first main surface of the semiconductor substrate has an impurity concentration that is the same as the impurity concentration of the plurality of second-conductivity-type high-concentration regions (23), and
a remaining third second-conductivity-type region (22) has an impurity concentration that is the same as the impurity concentration of the second semiconductor region (22).
With respect to claim 12, the device element structure of KABAYASHI further includes a plurality of second-conductivity-type high-concentration regions (3) selectively provided in the first semiconductor region (15), positioned closer to the second main surface of the semiconductor substrate than are bottoms of the plurality of trenches (19), the plurality of second-conductivity-type high-concentration regions (3) having an impurity concentration higher than an impurity concentration of the second semiconductor region (16), and
the bottoms of the plurality of second-conductivity-type voltage withstanding regions (8) are located deeper from the first main surface of the semiconductor substrate than are bottoms the plurality of second-conductivity-type high-concentration regions.,
With respect to claim 13, the device element structure of KOBAYASHI further includes a plurality of second-conductivity-type high-concentration regions (3) selectively provided in the first semiconductor region (15), positioned closer to the second main surface of the semiconductor substrate than are bottoms of the plurality of trenches (19), the plurality of second-conductivity-type high-concentration regions (3) having an impurity concentration higher than an impurity concentration of the second semiconductor region (16), and
the bottoms of the plurality of second-conductivity-type voltage withstanding regions (8) are located shallower from the first main surface of the semiconductor substrate than are bottoms the plurality of second-conductivity-type high-concentration regions (3).
With respect to claims 14-15, the plurality of second-conductivity-type high-concentration regions (3) includes:
a plurality of first high-concentration regions (3a) each facing a bottom of a respective one of the plurality of trenches (19) in the depth direction, and
a plurality of second high-concentration regions (3) each in contact with the second semiconductor region (16) and separate from both the plurality of first high-concentration regions (3a) and the plurality of trenches (19).
With respect to claim 16, in view of MIYAKE, the plurality of second-conductivity-type regions included in each of the plurality of second- conductivity-type voltage withstanding regions (24) are directly adjacent to one another in the depth direction (z) and are each directly adjacent to the second portion in the radial direction.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI ‘688 in view of MIYAKE ‘960 and WAKIMOTO et al. (US. Pub. No. 2017/0221714).
With respect to claim 19, KOBAYASHI teaches a semiconductor device having an active region (102) through which a main current flows and a termination region (101) surrounding a periphery of the active region, as claimed, the semiconductor device including:
a semiconductor substrate containing a semiconductor (SiC) having a bandgap wider than a bandgap of silicon, the semiconductor substrate having a first main surface (top) and a second main surface (bottom) opposite to each other, the semiconductor substrate including a first- conductivity-type epitaxial layer that forms the first main surface of the semiconductor substrate;
a first semiconductor region (15) of a first conductivity type (n), provided in the semiconductor substrate;
a second semiconductor region (16) of a second conductivity type (p), selectivity provided in the semiconductor substrate in the active region (102), between the first main surface of the semiconductor substrate and the first semiconductor region (15);
a device element structure formed in the semiconductor substrate in the active region (102), the device element structure having a pn junction between the second semiconductor region (16) and the first semiconductor region (15);
a first electrode (22) electrically connected to the second semiconductor region (16);
a second electrode (not shown) provided on the second main surface (bottom) of the semiconductor substrate; and
a plurality of second-conductivity-type voltage withstanding regions (8) each selectively provided in the semiconductor substrate in the termination region (101), between the first main surface (top) of the semiconductor substrate and the first semiconductor region, separate from the device element structure, the plurality of second-conductivity-type voltage withstanding regions (8) concentrically surrounding the periphery of the active region (102) to form concentric circles in a plan view of the semiconductor device, and being each provided separate from one another in a radial direction of the concentric circles,
wherein the device element structure includes:
a plurality of third semiconductor regions (17) of the first conductivity type (n), selectively provided in the semiconductor substrate, between the first main surface (top) of the semiconductor substrate and the second semiconductor region (16);
a plurality of trenches (19) penetrating through the plurality of third semiconductor regions (17) and the second semiconductor region (17), and reaching the first semiconductor region (15);
a plurality of gate electrodes (21) that are respectively provided in the plurality of trenches via a respective one of a plurality of gate insulating films (19a); and
a plurality of fourth semiconductor regions (18) of the second conductivity type (p), selectively provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and the second semiconductor region (16), the plurality of fourth semiconductor regions (18) having an impurity concentration (p+) higher than an impurity concentration (p) of the second semiconductor region (16),
the first main surface (top) of the semiconductor substrate is a flat surface spanning both the active region (102) and the termination region (101),
the second semiconductor region (16) and the plurality of second-conductivity-type voltage withstanding regions (8) are impurity diffusion regions, each of which is selectively provided in a first portion (III) of the first-conductivity-type epitaxial layer,
the first semiconductor region (15) is a second portion of the first-conductivity-type epitaxial layer excluding the first portion (III) of the first-conductivity-type epitaxial layer, the second portion including regions,
each of which is provided between a corresponding two of the plurality of second-conductivity-type voltage withstanding regions (8) that are adjacent to each other and reaches the first main surface of the semiconductor substrate, each of the plurality of second-conductivity-type voltage withstanding regions (8) is formed by a plurality of second-conductivity-type regions (8) that are in a depth direction (z) orthogonal to the first main surface of the semiconductor substrate,
the second semiconductor region (16) includes a lower second semiconductor region provided below each of the plurality of fourth semiconductor regions (18) in the depth direction, and an upper second semiconductor region provided on the lower second semiconductor region below the plurality of third semiconductor region (17) in the depth direction (z), an impurity concentration of the second semiconductor region (16) being lower than impurity concentrations of the at least a portion of each of the plurality of second-conductivity-type voltage withstanding regions (8). (See FIGs. 1-3, 9).
Thus, KOBAYASHI is shown to teach all the features of the claim with the exception of explicitly disclosing each of the plurality of second-conductivity-type voltage withstanding regions is formed by a plurality of second-conductivity-type regions that are stacked upon one another; and an impurity concentration of the lower second semiconductor region being lower than impurity concentrations of the upper second semiconductor region.
However, MIYAKE teaches a semiconductor device including:
each of the plurality of second-conductivity-type voltage withstanding regions (24) is formed by a plurality of second-conductivity-type regions (p) that are stacked upon one another in a depth direction (z) orthogonal to the first main surface of the semiconductor substrate.
(See FIGs. 1-3).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the voltage withstanding regions of KOBAYASHI ‘688 comprising the plurality of second-conductivity-type regions that are stacked upon one another in a depth direction (z) orthogonal to the first main surface of the semiconductor substrate as taught by MIYAKE to enable operating with high breakdown voltage.
Further, WAKIMOTO teaches a semiconductor device including:
a second semiconductor region (4) includes a lower second semiconductor region (4a) provided below each of the plurality of fourth semiconductor regions (6) in the depth direction (z), and an upper second semiconductor region (13) provided on the lower second semiconductor region (4a) below the plurality of third semiconductor region (5) in the depth direction (z), an impurity concentration of the lower second semiconductor region (4a) being lower than impurity concentrations of the upper second semiconductor region (13). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second semiconductor region of KOBAYASHI having impurity concentration of the lower second semiconductor region being lower than impurity concentrations of the upper second semiconductor region as taught by WAKIMOTO to reduce on-resistance without changing the gate threshold voltage.
With respect to claim 20, the impurity concentration of the lower second semiconductor region of KOBAYASHI is lower than an impurity concentration of one of the plurality of second-conductivity-type regions (8) included in a respective one of the plurality of second-conductivity-type voltage withstanding regions.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893
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