DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/12/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1).
As to claim 1, Chang et al. teaches a display device comprising: display pixels formed in an image display area of a display panel ([0034]: display 100 having light emitting pixels. The display 100 includes an active display area 110); a gate driving circuit formed in the image display area and the gate driving circuit being configured to supply gate signals to the display pixels ([0034-0035]: The GIP circuits 112 are provided in the array of the pixels 116. GIP circuits 112 supply gate signals to gate lines 114 that each of the pixels 116); a display driving circuit configured to supply a data voltage to data lines in the image display area through fan-out lines arranged in a non-display area of the display panel ([0039]: data driver 108 may supply the image data to the pixels 116 through the data lines 120;[0045], Fig. 1) and configured to supply gate control signals to the gate driving circuit through gate control lines arranged in the non-display area ([0039]: data driver 108 supplies a clock signal to the GIP circuits 112 over the clock lines 118); and wherein at least one gate control line of the gate control lines (318 in Fig. 3A) intersects one or more fan-out lines of the fan-out lines (320a in Fig. 3A) in one side direction of the image display area ([0057]: display area) corresponding to an arrangement direction of the display driving circuit ([0034]: data driver 108; [0058]), but does not explicitly disclose gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view, and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit.
However, Park et al. teaches gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view ( [0125]: display element DE1 at least partially overlap the gate driving circuit unit GDC in a plan view;[0150];[0154]: emission area EA1 of the display element DE1;[0172]: display element overlap gate driving circuit; [0175]), and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit ([0075-0076]: each of the first clock pad CLP1, the second clock pad CLP2, the first scan pad SP1, and the second scan pad SP2 may be plural. First clock pad CLP1 is connected to a plurality of gate driving circuit units GDC and transfers first clock signal to the plurality of gate driving circuit units GDC; [0078]: first scan pad SP1 connected to gate driving circuit unit, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. with gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view, and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit as taught by Park et al. in order to provide display apparatus in which a non-display area is reduced.
As to claim 2, Chang et al. in view of Park et al. teaches the display device of claim 1, wherein the at least one gate control line of the gate control lines (Chang et al., 318 in Fig. 3A) intersects one or more data lines of the data lines (Chang et al., data line 320a in Fig. 3A;[0062]: data lines) in the image display area (Chang et al., [0057]: display area) in one side direction corresponding to the arrangement direction of the display driving circuit (Chang et al.;[0034]: data driver 108; [0058]).
As to claim 3, Chang et al. in view of Park et al. teaches the display device of claim 2, wherein
the gate control lines include a gate start signal transmission line (Chang et al., first 318 line in Fig. 3A)
and a plurality of clock signal transmission lines (Chang et al., second and third 318 line in Fig. 3A;
[0039]: supplies a clock signal to the GIP circuits over the clock lines); and the one or more data lines
(Chang et al., data line 320a, 320b, 320d in Fig. 3A; [0062]: data lines) intersect one or more signal
transmission lines of the gate start signal transmission line and the plurality of clock signal transmission
lines, or intersect the one or more fan-out lines (note the word “or” recited in the claim: the one or
more data lines (Chang et al., data line 320a, 320b, 320d in Fig. 3A; [0062]: data lines) intersect one or
more signal transmission lines of the gate start signal transmission line (Chang et al., first 318 line in Fig.
3A) and the plurality of clock signal transmission lines (Chang et al., second and third 318 line in Fig. 3A;
[0039]: supplies a clock signal to the GIP circuits over the clock lines).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1) and further in view of Ka et al. (US 2019/0340974 A1).
As to claim 4, Chang et al. in view of Park et al. teaches the display device of claim 2, but does not explicitly disclose wherein a formation width of display pixels arranged in a preset first plane area among the display pixels arranged in the image display area in one direction is formed as a first width that is a reference width, a formation width of display pixels arranged in a preset second plane area among the display pixels arranged in the image display area in one direction is formed as a second width smaller than the first width, and a formation width of display pixels arranged in a preset third plane area among the display pixels arranged in the image display area in one direction is formed as a third width greater than the first width. However, Ka et al. teaches wherein a formation width of display pixels arranged in a preset first plane area among the display pixels arranged in the image display area in one direction is formed as a first width that is a reference width ([0090]: pixel region AA2 and pixel region AA3 have different widths), a formation width of display pixels arranged in a preset second plane area among the display pixels arranged in the image display area in one direction is formed as a second width smaller than the first width ([0090]: pixel region AA2 and pixel region AA3 have different widths (i.e. one of the pixels regions has second width smaller than first width of the other pixel region)), and a formation width of display pixels arranged in a preset third plane area among the display pixels arranged in the image display area in one direction is formed as a third width greater than the first width ([0090]: pixel regions AA1, AA2, and AA3. Pixel region AA1 occupies the widest area). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that a formation width of display pixels arranged in a preset first plane area among the display pixels arranged in the image display area in one direction is formed as a first width that is a reference width, a formation width of display pixels arranged in a preset second plane area among the display pixels arranged in the image display area in one direction is formed as a second width smaller than the first width, and a formation width of display pixels arranged in a preset third plane area among the display pixels arranged in the image display area in one direction is formed as a third width greater than the first width as taught by Ka et al. in order to provide a display device having excellent or improved image quality.
As to claim 5, Chang et al. in view of Park et al. and Ka et al. teaches the display device of
claim 4, wherein the one or more data lines (Chang et al., data line 320a in Fig. 3A; [0062]: data
lines) intersect at least one gate control line of the gate control lines (Chang et al., 318 in Fig. 3A) in
an arrangement area of the display pixels in the preset third plane area of the image display area (Chang
et al., [0052]: active display area include array of emissive pixels).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1) and further in view of Kim (US 2023/0014863 A1), hereinafter Kim (’63).
As to claim 10, Chang et al. in view of Park et al. teaches the display device of claim 1, but does not explicitly disclose wherein at least one driving voltage line of the driving voltage lines intersect the one or more fan-out lines in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit. However, Kim (’63) teaches wherein at least one driving voltage line of the driving voltage lines (driving voltage line VDDL in Figs. 12-13;[0180]: driving voltage line VDDL) intersect the one or more fan-out lines (FOL line in Figs. 12-13;[0164]: fan-out lines FOL) in one side direction of the image display area (display area DA in Fig. 12;[0064]: display area DA) corresponding to an arrangement direction of the display driving circuit (display driver 220 in Fig. 12; [0067]: display driver 220).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that at least one driving voltage line of the driving voltage lines intersect the one or more fan-out lines in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit as taught by Kim(’63) in order to provide a display device capable of reducing the size of a non-display area.
As to claim 11, Chang et al. in view of Park et al. teaches the display device as discussed above, but does not explicitly disclose wherein the at least one driving voltage line of the driving voltage lines intersect one or more data lines of the data lines in the image display area in one side direction corresponding to the arrangement direction of the display driving circuit. However, Kim(’63) teaches wherein at least one driving voltage line of the driving voltage lines (driving voltage line VDDL in Figs. 12-13;[0180]: driving voltage line VDDL) intersect one or more data lines of the data lines (DL1, DL2 lines in Figs. 12-13;[0177]: data lines DL1, DL2, DL3) in the image display area (display area DA in Fig. 12;[0064]: display area DA) in one side direction corresponding to an arrangement direction of the display driving circuit (display driver 220 in Fig. 12; [0067]: display driver 220).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that the at least one driving voltage line of the driving voltage lines intersect one or more data lines of the data lines in the image display area in one side direction corresponding to the arrangement direction of the display driving circuit as taught by Kim(’63) in order to provide a display device capable of reducing the size of a non-display area.
As to claim 12, Chang et al. in view of Park et al. teaches the display device as discussed above, but does not explicitly disclose wherein in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, electrostatic pattern lines to which a constant voltage is applied are between the at least one driving voltage line and the one or more fan-out lines or the data lines that intersect each other. However, Kim(’63) teaches wherein in an intersection area in which the at least driving voltage line (driving voltage line VDDL in Fig. 10;[0166]: driving voltage line VDDL) and the one or more fan-out lines or the data lines intersect ([0166]: driving voltage line VDDL overlaps the fan-out lines FOL), electrostatic pattern lines to which a constant voltage is applied ([0173]: low-potential line VSSL prevents static electricity) are between the at least one driving voltage line (driving voltage line VDDL in Fig. 10;[0166]: driving voltage line VDDL) and the one or more fan-out lines or the data lines that intersect each other([0166]: driving voltage line VDDL overlaps the fan-out lines FOL). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, electrostatic pattern lines to which a constant voltage is applied are between the at least one driving voltage line and the one or more fan-out lines or the data lines that intersect each other as taught by Kim(’63) in order to reduce signal interference.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1) in view of Kim (US 2023/0014863 A1), hereinafter Kim (’63), and further in view of Ko et al. (KR 10-2021-0016003, English machine translation mailed on 01/02/2026 is used in the rejection).
As to claim 14, Chang et al. in view of Park et al. and Kim(’63) teaches the display device of claim 11, but does not explicitly disclose wherein in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, an organic insulating pattern layer is formed between the at least one driving voltage line and the one or more fan-out lines or the data line that intersect each other.
However, Ko et al. teaches wherein in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect ([0040];[0051]: data line intersecting driving voltage line), an organic insulating pattern layer (ILD3in Fig. 4;[0075]: insulating film ILD3 is organic insulating material) is formed between the at least one driving voltage line (driving voltage line 26 in Fig. 4) and the one or more fan-out lines or the data line that intersect each other (data line 16 in Fig. 4;[0040]: data line intersecting driving voltage line; [0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. and Kim(’63) such that in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, an organic insulating pattern layer is formed between the at least one driving voltage line and the one or more fan-out lines or the data line that intersect each other as taught by Ko et al. in order to prevent crosstalk.
As to claim 15, Chang et al. in view of Park et al. and Kim(’63) teaches the display device of claim 14, but does not explicitly disclose wherein in the intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, the organic insulating pattern layer covers the at least one driving voltage line, and the one or more fan-out lines or the data lines intersect the at least one driving voltage line with the organic insulating pattern layer interposed therebetween.
However, Ko et al. teaches wherein in the intersection area in which the at least driving voltage line (driving voltage line 26 in Fig. 4) and the one or more fan-out lines or the data lines intersect ([0040];[0051]: data line intersecting driving voltage line), the organic insulating pattern layer (ILD3 in Fig. 4;[0075]: insulating film ILD3 is organic insulating material) covers the at least one driving voltage line (driving voltage line 26 in Fig. 4), and the one or more fan-out lines or the data lines intersect the at least one driving voltage line ([0040]: data line intersecting driving voltage line) with the organic insulating pattern layer (ILD3 in Fig. 4;[0075]: insulating film ILD3 is organic insulating material) interposed therebetween ([0054]; Fig. 4 shows insulating film ILD3 between data line 16 and driving voltage line 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. and Kim(’63) such that in the intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, the organic insulating pattern layer covers the at least one driving voltage line, and the one or more fan-out lines or the data lines intersect the at least one driving voltage line with the organic insulating pattern layer interposed therebetween as taught by Ko et al. in order to prevent crosstalk.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1) and further in view of Ko et al. (KR 10-2021-0016003, English machine translation mailed on 01/02/2026 is used in the rejection).
As to claim 16, Chang et al. teaches a display device comprising: a display panel including an image display area and a non-display area ([0051]: display 200 includes a bezel region 202 that is a non-display area and an active display area 210); display pixels in the image display area ([0034]: display 100 having light emitting pixels); a gate driving circuit formed in the image display area and the gate driving circuit being configured to supply gate signals to the display pixels ([0034-0035]: The GIP circuits 112 are provided in the array of the pixels 116. GIP circuits 112 supply gate signals to gate lines 114 of each of the pixels 116); a display driving circuit configured to supply a data voltage to data lines in the image display area through fan-out lines in the non-display area ([0039]: data driver 108 supplies the image data to the pixels 116 through the data lines 120;[0045], Fig. 1) and configured to supply gate control signals to the gate driving circuit through gate control lines in the non-display area ([0039]: data driver 108 supplies clock signal to the GIP circuits 112 over the clock lines 118); and wherein at least one gate control line of the gate control lines (318 in Fig. 3A) intersect one or more fan-out lines of the fan-out lines (320a in Fig. 3A) in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit ([0034]: data driver 108; [0058]), but does not explicitly disclose gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view, and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit. However, Park et al. teaches gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view ([0125]: display element DE1 at least partially overlap the gate driving circuit unit GDC in a plan view;[0150];[0154]: emission area EA1 of the first display element DE1;[0172]: display element overlap gate driving circuit;[0175]), and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit ([0075-0076]: each of the first clock pad CLP1, the second clock pad CLP2, the first scan pad SP1, and the second scan pad SP2 may be plural. First clock pad CLP1 is connected to a plurality of gate driving circuit units GDC and transfers first clock signal to the plurality of gate driving circuit units GDC; [0078]: first scan pad SP1 connected to gate driving circuit unit, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. with gate driving circuit overlapping one or more light emitting units of the display pixels in a plan view, and driving voltage lines arranged in the non-display area and configured to supply driving voltages to the gate driving circuit as taught by Park et al. in order to provide display apparatus in which a non-display area is reduced.
Chang et al. in view of Park et al. teaches the device as discussed above, but does not explicitly disclose at least one driving voltage line of the driving voltage lines intersect the one or more fan-out lines of the fan-out lines in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit. However, Ko et al. teaches at least one driving voltage line of the driving voltage lines intersect the one or more fan-out lines of the fan-out lines ([0040];[0051]: driving voltage line includes horizontal line intersect data line) in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit ([0027]: data driver 30, control unit 50 in Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that at least one driving voltage line of the driving voltage lines intersect the one or more fan-out lines of the fan-out lines in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit as taught by Ko et al. in order to prevent crosstalk.
As to claim 17, Chang et al. in view of Park et al. and Ko et al. teaches the display device of claim 16, wherein the at least one gate control line of the gate control lines (Chang et al., 318 in Fig. 3A) intersect one or more data lines of the data lines (Chang et al., data line 320a in Fig. 3A;[0062]: data lines) in the image display area (Chang et al., [0057]: display area) in one side direction corresponding to the arrangement direction of the display driving circuit (Chang et al., ;[0034]: data driver 108; [0058]).
As to claim 18, Chang et al. in view of Park et al. and Ko et al. teaches the display device of claim
17, wherein the gate control lines include a gate start signal transmission line (Chang et al., first 318 line
in Fig. 3A) and a plurality of clock signal transmission lines (Chang et al., second and third lines 318 in Fig.
3A; [0039]: supplies a clock signal to the GIP circuits over the clock lines), and one or more signal
transmission lines of the gate start signal transmission line (Chang et al., first 318 line in Fig. 3A) and the
plurality of clock signal transmission lines (Chang et al., second and third lines 318 in Fig. 3A; [0039]:
supplies a clock signal to the GIP circuits over the clock lines) intersect the one or more data lines or
intersect the one or more fan-out lines (Chang et al., data line 320a in Fig. 3A;[0062]: data lines).
As to claim 19, Chang et al. in view of Park et al. teaches the display device as discussed above,
but does not explicitly disclose wherein the at least one driving voltage line of the driving voltage lines
intersect one or more data lines of the data lines in the image display area in one side direction
corresponding to the arrangement direction of the display driving circuit.
However, Ko teaches wherein at least one driving voltage line of the driving voltage lines
intersect one or more data lines of the data lines in the image display area ([0040];[0051]: driving
voltage line includes horizontal line intersect data line) in one side direction corresponding to an
arrangement direction of the display driving circuit (30 in Fig. 1; [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. such that the at least one driving voltage line of the driving voltage lines intersect one or more data lines of the data lines in the image display area in one side direction corresponding to the arrangement direction of the display driving circuit as taught by Ko in order to prevent crosstalk.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0262302 A1) in view of Park et al. (US 2023/0030747 A1) in view of Ko et al. (KR 10-2021-0016003, English machine translation mailed on 01/02/2026 is used in the rejection) and further in view of Kim (US 2023/0014863 A1), hereinafter Kim (’63).
As to claim 20, Chang et al. in view of Park et al. and Ko et al. teaches the display device of claim 19, but does not explicitly disclose wherein in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, electrostatic pattern lines to which a constant voltage is applied are between the at least one driving voltage line and the one or more fan-out lines or the data lines that intersect each other.
However, Kim(’63) teaches wherein in an intersection area in which the at least driving voltage line (driving voltage line VDDL in Fig. 10;[0166]: driving voltage line VDDL) and the one or more fan-out lines or the data lines intersect ([0166]: driving voltage line VDDL overlaps the fan-out lines FOL), electrostatic pattern lines to which a constant voltage is applied ([0173]: low-potential line VSSL prevents static electricity) are between the at least one driving voltage line (driving voltage line VDDL in Fig. 10;[0166]: driving voltage line VDDL) and the one or more fan-out lines or the data lines that intersect each other([0166]: driving voltage line VDDL overlaps the fan-out lines FOL). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. in view of Park et al. and Ko et al. such that in an intersection area in which the at least driving voltage line and the one or more fan-out lines or the data lines intersect, electrostatic pattern lines to which a constant voltage is applied are between the at least one driving voltage line and the one or more fan-out lines or the data lines that intersect each other as taught by Kim (’63) in order to reduce signal interference.
Allowable Subject Matter
Claims 6-9 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments2
Applicant’s arguments with respect to claim(s) 1-5, 10-12, and 14-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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